1/*
2 * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#include <arch.h>
7#include <asm_macros.S>
8#include <common/bl_common.h>
9#include <common/debug.h>
10#include <cortex_a53.h>
11#include <cpu_macros.S>
12#include <lib/cpus/errata_report.h>
13#include <plat_macros.S>
14
15#if A53_DISABLE_NON_TEMPORAL_HINT
16#undef ERRATA_A53_836870
17#define ERRATA_A53_836870	1
18#endif
19
20	/* ---------------------------------------------
21	 * Disable L1 data cache and unified L2 cache
22	 * ---------------------------------------------
23	 */
24func cortex_a53_disable_dcache
25	mrs	x1, sctlr_el3
26	bic	x1, x1, #SCTLR_C_BIT
27	msr	sctlr_el3, x1
28	isb
29	ret
30endfunc cortex_a53_disable_dcache
31
32	/* ---------------------------------------------
33	 * Disable intra-cluster coherency
34	 * ---------------------------------------------
35	 */
36func cortex_a53_disable_smp
37	mrs	x0, CORTEX_A53_ECTLR_EL1
38	bic	x0, x0, #CORTEX_A53_ECTLR_SMP_BIT
39	msr	CORTEX_A53_ECTLR_EL1, x0
40	isb
41	dsb	sy
42	ret
43endfunc cortex_a53_disable_smp
44
45	/* ---------------------------------------------------
46	 * Errata Workaround for Cortex A53 Errata #819472.
47	 * This applies only to revision <= r0p1 of Cortex A53.
48	 * Due to the nature of the errata it is applied unconditionally
49	 * when built in, report it as applicable in this case
50	 * ---------------------------------------------------
51	 */
52func check_errata_819472
53#if ERRATA_A53_819472
54	mov x0, #ERRATA_APPLIES
55	ret
56#else
57	mov	x1, #0x01
58	b	cpu_rev_var_ls
59#endif
60endfunc check_errata_819472
61
62	/* ---------------------------------------------------
63	 * Errata Workaround for Cortex A53 Errata #824069.
64	 * This applies only to revision <= r0p2 of Cortex A53.
65	 * Due to the nature of the errata it is applied unconditionally
66	 * when built in, report it as applicable in this case
67	 * ---------------------------------------------------
68	 */
69func check_errata_824069
70#if ERRATA_A53_824069
71	mov x0, #ERRATA_APPLIES
72	ret
73#else
74	mov	x1, #0x02
75	b	cpu_rev_var_ls
76#endif
77endfunc check_errata_824069
78
79	/* --------------------------------------------------
80	 * Errata Workaround for Cortex A53 Errata #826319.
81	 * This applies only to revision <= r0p2 of Cortex A53.
82	 * Inputs:
83	 * x0: variant[4:7] and revision[0:3] of current cpu.
84	 * Shall clobber: x0-x17
85	 * --------------------------------------------------
86	 */
87func errata_a53_826319_wa
88	/*
89	 * Compare x0 against revision r0p2
90	 */
91	mov	x17, x30
92	bl	check_errata_826319
93	cbz	x0, 1f
94	mrs	x1, CORTEX_A53_L2ACTLR_EL1
95	bic	x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN
96	orr	x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH
97	msr	CORTEX_A53_L2ACTLR_EL1, x1
981:
99	ret	x17
100endfunc errata_a53_826319_wa
101
102func check_errata_826319
103	mov	x1, #0x02
104	b	cpu_rev_var_ls
105endfunc check_errata_826319
106
107	/* ---------------------------------------------------
108	 * Errata Workaround for Cortex A53 Errata #827319.
109	 * This applies only to revision <= r0p2 of Cortex A53.
110	 * Due to the nature of the errata it is applied unconditionally
111	 * when built in, report it as applicable in this case
112	 * ---------------------------------------------------
113	 */
114func check_errata_827319
115#if ERRATA_A53_827319
116	mov x0, #ERRATA_APPLIES
117	ret
118#else
119	mov	x1, #0x02
120	b	cpu_rev_var_ls
121#endif
122endfunc check_errata_827319
123
124	/* ---------------------------------------------------------------------
125	 * Disable the cache non-temporal hint.
126	 *
127	 * This ignores the Transient allocation hint in the MAIR and treats
128	 * allocations the same as non-transient allocation types. As a result,
129	 * the LDNP and STNP instructions in AArch64 behave the same as the
130	 * equivalent LDP and STP instructions.
131	 *
132	 * This is relevant only for revisions <= r0p3 of Cortex-A53.
133	 * From r0p4 and onwards, the bit to disable the hint is enabled by
134	 * default at reset.
135	 *
136	 * Inputs:
137	 * x0: variant[4:7] and revision[0:3] of current cpu.
138	 * Shall clobber: x0-x17
139	 * ---------------------------------------------------------------------
140	 */
141func a53_disable_non_temporal_hint
142	/*
143	 * Compare x0 against revision r0p3
144	 */
145	mov	x17, x30
146	bl	check_errata_disable_non_temporal_hint
147	cbz	x0, 1f
148	mrs	x1, CORTEX_A53_CPUACTLR_EL1
149	orr	x1, x1, #CORTEX_A53_CPUACTLR_EL1_DTAH
150	msr	CORTEX_A53_CPUACTLR_EL1, x1
1511:
152	ret	x17
153endfunc a53_disable_non_temporal_hint
154
155func check_errata_disable_non_temporal_hint
156	mov	x1, #0x03
157	b	cpu_rev_var_ls
158endfunc check_errata_disable_non_temporal_hint
159
160	/* --------------------------------------------------
161	 * Errata Workaround for Cortex A53 Errata #855873.
162	 *
163	 * This applies only to revisions >= r0p3 of Cortex A53.
164	 * Earlier revisions of the core are affected as well, but don't
165	 * have the chicken bit in the CPUACTLR register. It is expected that
166	 * the rich OS takes care of that, especially as the workaround is
167	 * shared with other erratas in those revisions of the CPU.
168	 * Inputs:
169	 * x0: variant[4:7] and revision[0:3] of current cpu.
170	 * Shall clobber: x0-x17
171	 * --------------------------------------------------
172	 */
173func errata_a53_855873_wa
174	/*
175	 * Compare x0 against revision r0p3 and higher
176	 */
177        mov     x17, x30
178        bl      check_errata_855873
179        cbz     x0, 1f
180
181	mrs	x1, CORTEX_A53_CPUACTLR_EL1
182	orr	x1, x1, #CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
183	msr	CORTEX_A53_CPUACTLR_EL1, x1
1841:
185	ret	x17
186endfunc errata_a53_855873_wa
187
188func check_errata_855873
189	mov	x1, #0x03
190	b	cpu_rev_var_hs
191endfunc check_errata_855873
192
193/*
194 * Errata workaround for Cortex A53 Errata #835769.
195 * This applies to revisions <= r0p4 of Cortex A53.
196 * This workaround is statically enabled at build time.
197 */
198func check_errata_835769
199	cmp	x0, #0x04
200	b.hi	errata_not_applies
201	/*
202	 * Fix potentially available for revisions r0p2, r0p3 and r0p4.
203	 * If r0p2, r0p3 or r0p4; check for fix in REVIDR, else exit.
204	 */
205	cmp	x0, #0x01
206	mov	x0, #ERRATA_APPLIES
207	b.ls	exit_check_errata_835769
208	/* Load REVIDR. */
209	mrs	x1, revidr_el1
210	/* If REVIDR[7] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */
211	tbz	x1, #7, exit_check_errata_835769
212errata_not_applies:
213	mov	x0, #ERRATA_NOT_APPLIES
214exit_check_errata_835769:
215	ret
216endfunc check_errata_835769
217
218/*
219 * Errata workaround for Cortex A53 Errata #843419.
220 * This applies to revisions <= r0p4 of Cortex A53.
221 * This workaround is statically enabled at build time.
222 */
223func check_errata_843419
224	mov	x1, #ERRATA_APPLIES
225	mov	x2, #ERRATA_NOT_APPLIES
226	cmp	x0, #0x04
227	csel	x0, x1, x2, ls
228	/*
229	 * Fix potentially available for revision r0p4.
230	 * If r0p4 check for fix in REVIDR, else exit.
231	 */
232	b.ne	exit_check_errata_843419
233	/* Load REVIDR. */
234	mrs	x3, revidr_el1
235	/* If REVIDR[8] is set (fix exists) set ERRATA_NOT_APPLIES, else exit. */
236	tbz	x3, #8, exit_check_errata_843419
237	mov	x0, x2
238exit_check_errata_843419:
239	ret
240endfunc check_errata_843419
241
242	/* --------------------------------------------------
243	 * Errata workaround for Cortex A53 Errata #1530924.
244	 * This applies to all revisions of Cortex A53.
245	 * --------------------------------------------------
246	 */
247func check_errata_1530924
248#if ERRATA_A53_1530924
249	mov	x0, #ERRATA_APPLIES
250#else
251	mov	x0, #ERRATA_MISSING
252#endif
253	ret
254endfunc check_errata_1530924
255
256	/* -------------------------------------------------
257	 * The CPU Ops reset function for Cortex-A53.
258	 * Shall clobber: x0-x19
259	 * -------------------------------------------------
260	 */
261func cortex_a53_reset_func
262	mov	x19, x30
263	bl	cpu_get_rev_var
264	mov	x18, x0
265
266
267#if ERRATA_A53_826319
268	mov	x0, x18
269	bl	errata_a53_826319_wa
270#endif
271
272#if ERRATA_A53_836870
273	mov	x0, x18
274	bl	a53_disable_non_temporal_hint
275#endif
276
277#if ERRATA_A53_855873
278	mov	x0, x18
279	bl	errata_a53_855873_wa
280#endif
281
282	/* ---------------------------------------------
283	 * Enable the SMP bit.
284	 * ---------------------------------------------
285	 */
286	mrs	x0, CORTEX_A53_ECTLR_EL1
287	orr	x0, x0, #CORTEX_A53_ECTLR_SMP_BIT
288	msr	CORTEX_A53_ECTLR_EL1, x0
289	isb
290	ret	x19
291endfunc cortex_a53_reset_func
292
293func cortex_a53_core_pwr_dwn
294	mov	x18, x30
295
296	/* ---------------------------------------------
297	 * Turn off caches.
298	 * ---------------------------------------------
299	 */
300	bl	cortex_a53_disable_dcache
301
302	/* ---------------------------------------------
303	 * Flush L1 caches.
304	 * ---------------------------------------------
305	 */
306	mov	x0, #DCCISW
307	bl	dcsw_op_level1
308
309	/* ---------------------------------------------
310	 * Come out of intra cluster coherency
311	 * ---------------------------------------------
312	 */
313	mov	x30, x18
314	b	cortex_a53_disable_smp
315endfunc cortex_a53_core_pwr_dwn
316
317func cortex_a53_cluster_pwr_dwn
318	mov	x18, x30
319
320	/* ---------------------------------------------
321	 * Turn off caches.
322	 * ---------------------------------------------
323	 */
324	bl	cortex_a53_disable_dcache
325
326	/* ---------------------------------------------
327	 * Flush L1 caches.
328	 * ---------------------------------------------
329	 */
330	mov	x0, #DCCISW
331	bl	dcsw_op_level1
332
333	/* ---------------------------------------------
334	 * Disable the optional ACP.
335	 * ---------------------------------------------
336	 */
337	bl	plat_disable_acp
338
339	/* ---------------------------------------------
340	 * Flush L2 caches.
341	 * ---------------------------------------------
342	 */
343	mov	x0, #DCCISW
344	bl	dcsw_op_level2
345
346	/* ---------------------------------------------
347	 * Come out of intra cluster coherency
348	 * ---------------------------------------------
349	 */
350	mov	x30, x18
351	b	cortex_a53_disable_smp
352endfunc cortex_a53_cluster_pwr_dwn
353
354#if REPORT_ERRATA
355/*
356 * Errata printing function for Cortex A53. Must follow AAPCS.
357 */
358func cortex_a53_errata_report
359	stp	x8, x30, [sp, #-16]!
360
361	bl	cpu_get_rev_var
362	mov	x8, x0
363
364	/*
365	 * Report all errata. The revision-variant information is passed to
366	 * checking functions of each errata.
367	 */
368	report_errata ERRATA_A53_819472, cortex_a53, 819472
369	report_errata ERRATA_A53_824069, cortex_a53, 824069
370	report_errata ERRATA_A53_826319, cortex_a53, 826319
371	report_errata ERRATA_A53_827319, cortex_a53, 827319
372	report_errata ERRATA_A53_835769, cortex_a53, 835769
373	report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
374	report_errata ERRATA_A53_843419, cortex_a53, 843419
375	report_errata ERRATA_A53_855873, cortex_a53, 855873
376	report_errata ERRATA_A53_1530924, cortex_a53, 1530924
377
378	ldp	x8, x30, [sp], #16
379	ret
380endfunc cortex_a53_errata_report
381#endif
382
383	/* ---------------------------------------------
384	 * This function provides cortex_a53 specific
385	 * register information for crash reporting.
386	 * It needs to return with x6 pointing to
387	 * a list of register names in ascii and
388	 * x8 - x15 having values of registers to be
389	 * reported.
390	 * ---------------------------------------------
391	 */
392.section .rodata.cortex_a53_regs, "aS"
393cortex_a53_regs:  /* The ascii list of register names to be reported */
394	.asciz	"cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", \
395		"cpuactlr_el1", ""
396
397func cortex_a53_cpu_reg_dump
398	adr	x6, cortex_a53_regs
399	mrs	x8, CORTEX_A53_ECTLR_EL1
400	mrs	x9, CORTEX_A53_MERRSR_EL1
401	mrs	x10, CORTEX_A53_L2MERRSR_EL1
402	mrs	x11, CORTEX_A53_CPUACTLR_EL1
403	ret
404endfunc cortex_a53_cpu_reg_dump
405
406declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
407	cortex_a53_reset_func, \
408	cortex_a53_core_pwr_dwn, \
409	cortex_a53_cluster_pwr_dwn
410