1/*
2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <cortex_a75.h>
10#include <cpuamu.h>
11#include <cpu_macros.S>
12
13/* Hardware handled coherency */
14#if HW_ASSISTED_COHERENCY == 0
15#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
16#endif
17
18	/* --------------------------------------------------
19	 * Errata Workaround for Cortex A75 Errata #764081.
20	 * This applies only to revision r0p0 of Cortex A75.
21	 * Inputs:
22	 * x0: variant[4:7] and revision[0:3] of current cpu.
23	 * Shall clobber: x0-x17
24	 * --------------------------------------------------
25	 */
26func errata_a75_764081_wa
27	/*
28	 * Compare x0 against revision r0p0
29	 */
30	mov	x17, x30
31	bl	check_errata_764081
32	cbz	x0, 1f
33	mrs	x1, sctlr_el3
34	orr	x1, x1 ,#SCTLR_IESB_BIT
35	msr	sctlr_el3, x1
36	isb
371:
38	ret	x17
39endfunc errata_a75_764081_wa
40
41func check_errata_764081
42	mov	x1, #0x00
43	b	cpu_rev_var_ls
44endfunc check_errata_764081
45
46	/* --------------------------------------------------
47	 * Errata Workaround for Cortex A75 Errata #790748.
48	 * This applies only to revision r0p0 of Cortex A75.
49	 * Inputs:
50	 * x0: variant[4:7] and revision[0:3] of current cpu.
51	 * Shall clobber: x0-x17
52	 * --------------------------------------------------
53	 */
54func errata_a75_790748_wa
55	/*
56	 * Compare x0 against revision r0p0
57	 */
58	mov	x17, x30
59	bl	check_errata_790748
60	cbz	x0, 1f
61	mrs	x1, CORTEX_A75_CPUACTLR_EL1
62	orr	x1, x1 ,#(1 << 13)
63	msr	CORTEX_A75_CPUACTLR_EL1, x1
64	isb
651:
66	ret	x17
67endfunc errata_a75_790748_wa
68
69func check_errata_790748
70	mov	x1, #0x00
71	b	cpu_rev_var_ls
72endfunc check_errata_790748
73
74	/* -------------------------------------------------
75	 * The CPU Ops reset function for Cortex-A75.
76	 * -------------------------------------------------
77	 */
78func cortex_a75_reset_func
79	mov	x19, x30
80	bl	cpu_get_rev_var
81	mov	x18, x0
82
83#if ERRATA_A75_764081
84	mov	x0, x18
85	bl	errata_a75_764081_wa
86#endif
87
88#if ERRATA_A75_790748
89	mov	x0, x18
90	bl	errata_a75_790748_wa
91#endif
92
93#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
94	cpu_check_csv2	x0, 1f
95	adr	x0, wa_cve_2017_5715_bpiall_vbar
96	msr	vbar_el3, x0
97	isb
981:
99#endif
100
101#if WORKAROUND_CVE_2018_3639
102	mrs	x0, CORTEX_A75_CPUACTLR_EL1
103	orr	x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE
104	msr	CORTEX_A75_CPUACTLR_EL1, x0
105	isb
106#endif
107
108#if ERRATA_DSU_798953
109	bl	errata_dsu_798953_wa
110#endif
111
112#if ERRATA_DSU_936184
113	bl	errata_dsu_936184_wa
114#endif
115
116#if ENABLE_AMU
117	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
118	mrs	x0, actlr_el3
119	orr	x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
120	msr	actlr_el3, x0
121	isb
122
123	/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
124	mrs	x0, actlr_el2
125	orr	x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT
126	msr	actlr_el2, x0
127	isb
128
129	/* Enable group0 counters */
130	mov	x0, #CORTEX_A75_AMU_GROUP0_MASK
131	msr	CPUAMCNTENSET_EL0, x0
132	isb
133
134	/* Enable group1 counters */
135	mov	x0, #CORTEX_A75_AMU_GROUP1_MASK
136	msr	CPUAMCNTENSET_EL0, x0
137	isb
138#endif
139	ret	x19
140endfunc cortex_a75_reset_func
141
142func check_errata_cve_2017_5715
143	cpu_check_csv2	x0, 1f
144#if WORKAROUND_CVE_2017_5715
145	mov	x0, #ERRATA_APPLIES
146#else
147	mov	x0, #ERRATA_MISSING
148#endif
149	ret
1501:
151	mov	x0, #ERRATA_NOT_APPLIES
152	ret
153endfunc check_errata_cve_2017_5715
154
155func check_errata_cve_2018_3639
156#if WORKAROUND_CVE_2018_3639
157	mov	x0, #ERRATA_APPLIES
158#else
159	mov	x0, #ERRATA_MISSING
160#endif
161	ret
162endfunc check_errata_cve_2018_3639
163
164	/* ---------------------------------------------
165	 * HW will do the cache maintenance while powering down
166	 * ---------------------------------------------
167	 */
168func cortex_a75_core_pwr_dwn
169	/* ---------------------------------------------
170	 * Enable CPU power down bit in power control register
171	 * ---------------------------------------------
172	 */
173	mrs	x0, CORTEX_A75_CPUPWRCTLR_EL1
174	orr	x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK
175	msr	CORTEX_A75_CPUPWRCTLR_EL1, x0
176	isb
177	ret
178endfunc cortex_a75_core_pwr_dwn
179
180#if REPORT_ERRATA
181/*
182 * Errata printing function for Cortex A75. Must follow AAPCS.
183 */
184func cortex_a75_errata_report
185	stp	x8, x30, [sp, #-16]!
186
187	bl	cpu_get_rev_var
188	mov	x8, x0
189
190	/*
191	 * Report all errata. The revision-variant information is passed to
192	 * checking functions of each errata.
193	 */
194	report_errata ERRATA_A75_764081, cortex_a75, 764081
195	report_errata ERRATA_A75_790748, cortex_a75, 790748
196	report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715
197	report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639
198	report_errata ERRATA_DSU_798953, cortex_a75, dsu_798953
199	report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184
200
201	ldp	x8, x30, [sp], #16
202	ret
203endfunc cortex_a75_errata_report
204#endif
205
206	/* ---------------------------------------------
207	 * This function provides cortex_a75 specific
208	 * register information for crash reporting.
209	 * It needs to return with x6 pointing to
210	 * a list of register names in ascii and
211	 * x8 - x15 having values of registers to be
212	 * reported.
213	 * ---------------------------------------------
214	 */
215.section .rodata.cortex_a75_regs, "aS"
216cortex_a75_regs:  /* The ascii list of register names to be reported */
217	.asciz	"cpuectlr_el1", ""
218
219func cortex_a75_cpu_reg_dump
220	adr	x6, cortex_a75_regs
221	mrs	x8, CORTEX_A75_CPUECTLR_EL1
222	ret
223endfunc cortex_a75_cpu_reg_dump
224
225declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \
226	cortex_a75_reset_func, \
227	check_errata_cve_2017_5715, \
228	CPU_NO_EXTRA2_FUNC, \
229	cortex_a75_core_pwr_dwn
230