1/*
2 * Copyright (c) 2019, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <asm_macros.S>
8#include <cortex_a76ae.h>
9#include <cpu_macros.S>
10
11/* Hardware handled coherency */
12#if HW_ASSISTED_COHERENCY == 0
13#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled"
14#endif
15
16/* 64-bit only core */
17#if CTX_INCLUDE_AARCH32_REGS == 1
18#error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
19#endif
20
21	/* ---------------------------------------------
22	 * HW will do the cache maintenance while powering down
23	 * ---------------------------------------------
24	 */
25func cortex_a76ae_core_pwr_dwn
26	/* ---------------------------------------------
27	 * Enable CPU power down bit in power control register
28	 * ---------------------------------------------
29	 */
30	mrs	x0, CORTEX_A76AE_CPUPWRCTLR_EL1
31	orr	x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK
32	msr	CORTEX_A76AE_CPUPWRCTLR_EL1, x0
33	isb
34	ret
35endfunc cortex_a76ae_core_pwr_dwn
36
37#if REPORT_ERRATA
38/*
39 * Errata printing function for Cortex-A76AE. Must follow AAPCS.
40 */
41func cortex_a76ae_errata_report
42	ret
43endfunc cortex_a76ae_errata_report
44#endif	/* REPORT_ERRATA */
45
46	/* ---------------------------------------------
47	 * This function provides cortex_a76ae specific
48	 * register information for crash reporting.
49	 * It needs to return with x6 pointing to
50	 * a list of register names in ascii and
51	 * x8 - x15 having values of registers to be
52	 * reported.
53	 * ---------------------------------------------
54	 */
55.section .rodata.cortex_a76ae_regs, "aS"
56cortex_a76ae_regs:  /* The ASCII list of register names to be reported */
57	.asciz	"cpuectlr_el1", ""
58
59func cortex_a76ae_cpu_reg_dump
60	adr	x6, cortex_a76ae_regs
61	mrs	x8, CORTEX_A76AE_CPUECTLR_EL1
62	ret
63endfunc cortex_a76ae_cpu_reg_dump
64
65declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, CPU_NO_RESET_FUNC, \
66	cortex_a76ae_core_pwr_dwn
67