1/*
2 * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_a77.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13
14/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
19/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
24	/* --------------------------------------------------
25	 * Errata Workaround for Cortex A77 Errata #1508412.
26	 * This applies only to revision <= r1p0 of Cortex A77.
27	 * Inputs:
28	 * x0: variant[4:7] and revision[0:3] of current cpu.
29	 * Shall clobber: x0-x17
30	 * --------------------------------------------------
31	 */
32func errata_a77_1508412_wa
33	/*
34	 * Compare x0 against revision r1p0
35	 */
36	mov	x17, x30
37	bl	check_errata_1508412
38	cbz	x0, 3f
39	/*
40	 * Compare x0 against revision r0p0
41	 */
42	bl	check_errata_1508412_0
43	cbz	x0, 1f
44	ldr	x0, =0x0
45	msr	CORTEX_A77_CPUPSELR_EL3, x0
46	ldr 	x0, =0x00E8400000
47	msr	CORTEX_A77_CPUPOR_EL3, x0
48	ldr	x0, =0x00FFE00000
49	msr	CORTEX_A77_CPUPMR_EL3, x0
50	ldr	x0, =0x4004003FF
51	msr	CORTEX_A77_CPUPCR_EL3, x0
52	ldr	x0, =0x1
53	msr	CORTEX_A77_CPUPSELR_EL3, x0
54	ldr	x0, =0x00E8C00040
55	msr	CORTEX_A77_CPUPOR_EL3, x0
56	ldr	x0, =0x00FFE00040
57	msr	CORTEX_A77_CPUPMR_EL3, x0
58	b	2f
591:
60	ldr	x0, =0x0
61	msr	CORTEX_A77_CPUPSELR_EL3, x0
62	ldr	x0, =0x00E8400000
63	msr	CORTEX_A77_CPUPOR_EL3, x0
64	ldr	x0, =0x00FF600000
65	msr	CORTEX_A77_CPUPMR_EL3, x0
66	ldr	x0, =0x00E8E00080
67	msr	CORTEX_A77_CPUPOR2_EL3, x0
68	ldr	x0, =0x00FFE000C0
69	msr	CORTEX_A77_CPUPMR2_EL3, x0
702:
71	ldr	x0, =0x04004003FF
72	msr	CORTEX_A77_CPUPCR_EL3, x0
73	isb
743:
75	ret	x17
76endfunc errata_a77_1508412_wa
77
78func check_errata_1508412
79	mov	x1, #0x10
80	b	cpu_rev_var_ls
81endfunc check_errata_1508412
82
83func check_errata_1508412_0
84	mov	x1, #0x0
85	b	cpu_rev_var_ls
86endfunc check_errata_1508412_0
87
88	/* --------------------------------------------------
89	 * Errata Workaround for Cortex A77 Errata #1925769.
90	 * This applies to revision <= r1p1 of Cortex A77.
91	 * Inputs:
92	 * x0: variant[4:7] and revision[0:3] of current cpu.
93	 * Shall clobber: x0-x17
94	 * --------------------------------------------------
95	 */
96func errata_a77_1925769_wa
97	/* Compare x0 against revision <= r1p1 */
98	mov	x17, x30
99	bl	check_errata_1925769
100	cbz	x0, 1f
101
102	/* Set bit 8 in ECTLR_EL1 */
103	mrs	x1, CORTEX_A77_CPUECTLR_EL1
104	orr	x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8
105	msr	CORTEX_A77_CPUECTLR_EL1, x1
106	isb
1071:
108	ret	x17
109endfunc errata_a77_1925769_wa
110
111func check_errata_1925769
112	/* Applies to everything <= r1p1 */
113	mov	x1, #0x11
114	b	cpu_rev_var_ls
115endfunc check_errata_1925769
116
117	/* --------------------------------------------------
118	 * Errata Workaround for Cortex A77 Errata #1946167.
119	 * This applies to revision <= r1p1 of Cortex A77.
120	 * Inputs:
121	 * x0: variant[4:7] and revision[0:3] of current cpu.
122	 * Shall clobber: x0-x17
123	 * --------------------------------------------------
124	 */
125func errata_a77_1946167_wa
126	/* Compare x0 against revision <= r1p1 */
127	mov	x17, x30
128	bl	check_errata_1946167
129	cbz	x0, 1f
130
131	ldr	x0,=0x4
132	msr	CORTEX_A77_CPUPSELR_EL3,x0
133	ldr	x0,=0x10E3900002
134	msr	CORTEX_A77_CPUPOR_EL3,x0
135	ldr	x0,=0x10FFF00083
136	msr	CORTEX_A77_CPUPMR_EL3,x0
137	ldr	x0,=0x2001003FF
138	msr	CORTEX_A77_CPUPCR_EL3,x0
139
140	ldr	x0,=0x5
141	msr	CORTEX_A77_CPUPSELR_EL3,x0
142	ldr	x0,=0x10E3800082
143	msr	CORTEX_A77_CPUPOR_EL3,x0
144	ldr	x0,=0x10FFF00083
145	msr	CORTEX_A77_CPUPMR_EL3,x0
146	ldr	x0,=0x2001003FF
147	msr	CORTEX_A77_CPUPCR_EL3,x0
148
149	ldr	x0,=0x6
150	msr	CORTEX_A77_CPUPSELR_EL3,x0
151	ldr	x0,=0x10E3800200
152	msr	CORTEX_A77_CPUPOR_EL3,x0
153	ldr	x0,=0x10FFF003E0
154	msr	CORTEX_A77_CPUPMR_EL3,x0
155	ldr	x0,=0x2001003FF
156	msr	CORTEX_A77_CPUPCR_EL3,x0
157
158	isb
1591:
160	ret	x17
161endfunc errata_a77_1946167_wa
162
163func check_errata_1946167
164	/* Applies to everything <= r1p1 */
165	mov	x1, #0x11
166	b	cpu_rev_var_ls
167endfunc check_errata_1946167
168
169	/* --------------------------------------------------
170	 * Errata Workaround for Cortex A77 Errata #1791578.
171	 * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
172	 * x0: variant[4:7] and revision[0:3] of current cpu.
173	 * Shall clobber: x0-x17
174	 * --------------------------------------------------
175	 */
176func errata_a77_1791578_wa
177	/* Check workaround compatibility. */
178	mov	x17, x30
179	bl	check_errata_1791578
180	cbz	x0, 1f
181
182	/* Set bit 2 in ACTLR2_EL1 */
183	mrs     x1, CORTEX_A77_ACTLR2_EL1
184	orr	x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2
185	msr     CORTEX_A77_ACTLR2_EL1, x1
186	isb
1871:
188	ret	x17
189endfunc errata_a77_1791578_wa
190
191func check_errata_1791578
192	/* Applies to r0p0, r1p0, and r1p1 right now */
193	mov	x1, #0x11
194	b	cpu_rev_var_ls
195endfunc check_errata_1791578
196
197	/* -------------------------------------------------
198	 * The CPU Ops reset function for Cortex-A77.
199	 * Shall clobber: x0-x19
200	 * -------------------------------------------------
201	 */
202func cortex_a77_reset_func
203	mov	x19, x30
204	bl	cpu_get_rev_var
205	mov	x18, x0
206
207#if ERRATA_A77_1508412
208	mov	x0, x18
209	bl	errata_a77_1508412_wa
210#endif
211
212#if ERRATA_A77_1925769
213	mov	x0, x18
214	bl	errata_a77_1925769_wa
215#endif
216
217#if ERRATA_A77_1946167
218	mov	x0, x18
219	bl	errata_a77_1946167_wa
220#endif
221
222#if ERRATA_A77_1791578
223	mov	x0, x18
224	bl	errata_a77_1791578_wa
225#endif
226
227	ret	x19
228endfunc cortex_a77_reset_func
229
230	/* ---------------------------------------------
231	 * HW will do the cache maintenance while powering down
232	 * ---------------------------------------------
233	 */
234func cortex_a77_core_pwr_dwn
235	/* ---------------------------------------------
236	 * Enable CPU power down bit in power control register
237	 * ---------------------------------------------
238	 */
239	mrs	x0, CORTEX_A77_CPUPWRCTLR_EL1
240	orr	x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
241	msr	CORTEX_A77_CPUPWRCTLR_EL1, x0
242	isb
243	ret
244endfunc cortex_a77_core_pwr_dwn
245
246#if REPORT_ERRATA
247/*
248 * Errata printing function for Cortex-A77. Must follow AAPCS.
249 */
250func cortex_a77_errata_report
251	stp	x8, x30, [sp, #-16]!
252
253	bl	cpu_get_rev_var
254	mov	x8, x0
255
256	/*
257	 * Report all errata. The revision-variant information is passed to
258	 * checking functions of each errata.
259	 */
260	report_errata ERRATA_A77_1508412, cortex_a77, 1508412
261	report_errata ERRATA_A77_1925769, cortex_a77, 1925769
262	report_errata ERRATA_A77_1946167, cortex_a77, 1946167
263	report_errata ERRATA_A77_1791578, cortex_a77, 1791578
264
265	ldp	x8, x30, [sp], #16
266	ret
267endfunc cortex_a77_errata_report
268#endif
269
270
271	/* ---------------------------------------------
272	 * This function provides Cortex-A77 specific
273	 * register information for crash reporting.
274	 * It needs to return with x6 pointing to
275	 * a list of register names in ascii and
276	 * x8 - x15 having values of registers to be
277	 * reported.
278	 * ---------------------------------------------
279	 */
280.section .rodata.cortex_a77_regs, "aS"
281cortex_a77_regs:  /* The ascii list of register names to be reported */
282	.asciz	"cpuectlr_el1", ""
283
284func cortex_a77_cpu_reg_dump
285	adr	x6, cortex_a77_regs
286	mrs	x8, CORTEX_A77_CPUECTLR_EL1
287	ret
288endfunc cortex_a77_cpu_reg_dump
289
290declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \
291	cortex_a77_reset_func, \
292	cortex_a77_core_pwr_dwn
293