1/*
2 * Copyright (c) 2020, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <context.h>
10#include <cpu_macros.S>
11#include <cpuamu.h>
12#include <rainier.h>
13
14/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Rainier CPU must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
19/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Rainier CPU supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
24/* --------------------------------------------------
25 * Disable speculative loads if Rainier supports
26 * SSBS.
27 *
28 * Shall clobber: x0.
29 * --------------------------------------------------
30 */
31func rainier_disable_speculative_loads
32	/* Check if the PE implements SSBS */
33	mrs	x0, id_aa64pfr1_el1
34	tst	x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
35	b.eq	1f
36
37	/* Disable speculative loads */
38	msr	SSBS, xzr
39
401:
41	ret
42endfunc rainier_disable_speculative_loads
43
44func rainier_reset_func
45	mov	x19, x30
46
47	bl	rainier_disable_speculative_loads
48
49	/* Forces all cacheable atomic instructions to be near */
50	mrs	x0, RAINIER_CPUACTLR2_EL1
51	orr	x0, x0, #RAINIER_CPUACTLR2_EL1_BIT_2
52	msr	RAINIER_CPUACTLR2_EL1, x0
53	isb
54
55	bl	cpu_get_rev_var
56	mov	x18, x0
57
58#if ENABLE_AMU
59	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
60	mrs	x0, actlr_el3
61	orr	x0, x0, #RAINIER_ACTLR_AMEN_BIT
62	msr	actlr_el3, x0
63
64	/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
65	mrs	x0, actlr_el2
66	orr	x0, x0, #RAINIER_ACTLR_AMEN_BIT
67	msr	actlr_el2, x0
68
69	/* Enable group0 counters */
70	mov	x0, #RAINIER_AMU_GROUP0_MASK
71	msr	CPUAMCNTENSET_EL0, x0
72#endif
73
74	isb
75	ret	x19
76endfunc rainier_reset_func
77
78	/* ---------------------------------------------
79	 * HW will do the cache maintenance while powering down
80	 * ---------------------------------------------
81	 */
82func rainier_core_pwr_dwn
83	/* ---------------------------------------------
84	 * Enable CPU power down bit in power control register
85	 * ---------------------------------------------
86	 */
87	mrs	x0, RAINIER_CPUPWRCTLR_EL1
88	orr	x0, x0, #RAINIER_CORE_PWRDN_EN_MASK
89	msr	RAINIER_CPUPWRCTLR_EL1, x0
90	isb
91	ret
92endfunc rainier_core_pwr_dwn
93
94#if REPORT_ERRATA
95/*
96 * Errata printing function for Rainier. Must follow AAPCS.
97 */
98func rainier_errata_report
99	stp	x8, x30, [sp, #-16]!
100
101	bl	cpu_get_rev_var
102	mov	x8, x0
103
104	ldp	x8, x30, [sp], #16
105	ret
106endfunc rainier_errata_report
107#endif
108
109	/* ---------------------------------------------
110	 * This function provides Rainier specific
111	 * register information for crash reporting.
112	 * It needs to return with x6 pointing to
113	 * a list of register names in ascii and
114	 * x8 - x15 having values of registers to be
115	 * reported.
116	 * ---------------------------------------------
117	 */
118.section .rodata.rainier_regs, "aS"
119rainier_regs:  /* The ascii list of register names to be reported */
120	.asciz	"cpuectlr_el1", ""
121
122func rainier_cpu_reg_dump
123	adr	x6, rainier_regs
124	mrs	x8, RAINIER_CPUECTLR_EL1
125	ret
126endfunc rainier_cpu_reg_dump
127
128declare_cpu_ops rainier, RAINIER_MIDR, \
129	rainier_reset_func, \
130	rainier_core_pwr_dwn
131