1 /* 2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <lib/el3_runtime/pubsub.h> 12 #include <lib/extensions/sve.h> 13 14 /* 15 * Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation. 16 * VECTOR_SIZE = (LEN+1) * 128 17 */ 18 #define CONVERT_SVE_LENGTH(x) (((x / 128) - 1)) 19 sve_supported(void)20static bool sve_supported(void) 21 { 22 uint64_t features; 23 24 features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT; 25 return (features & ID_AA64PFR0_SVE_MASK) == 1U; 26 } 27 sve_enable(cpu_context_t * context)28void sve_enable(cpu_context_t *context) 29 { 30 u_register_t cptr_el3; 31 32 if (!sve_supported()) { 33 return; 34 } 35 36 cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3); 37 38 /* Enable access to SVE functionality for all ELs. */ 39 cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT); 40 write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3); 41 42 /* Restrict maximum SVE vector length (SVE_VECTOR_LENGTH+1) * 128. */ 43 write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3, 44 (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(512))); 45 } 46 sve_disable(cpu_context_t * context)47void sve_disable(cpu_context_t *context) 48 { 49 u_register_t reg; 50 el3_state_t *state; 51 52 /* Make sure SME is implemented in hardware before continuing. */ 53 if (!sve_supported()) { 54 return; 55 } 56 57 /* Get the context state. */ 58 state = get_el3state_ctx(context); 59 60 /* Disable SVE and FPU since they share registers. */ 61 reg = read_ctx_reg(state, CTX_CPTR_EL3); 62 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ 63 reg |= TFP_BIT; /* Trap FPU/SIMD */ 64 write_ctx_reg(state, CTX_CPTR_EL3, reg); 65 } 66