1/* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <lib/xlat_tables/xlat_tables_v2.h> 10#include <platform_def.h> 11 12 .global enable_mpu_direct_el2 13 14 /* void enable_mmu_direct_el2(unsigned int flags) */ 15func enable_mpu_direct_el2 16#if ENABLE_ASSERTIONS 17 mrs x1, sctlr_el2 18 tst x1, #SCTLR_M_BIT 19 ASM_ASSERT(eq) 20#endif 21 mov x7, x0 22 adrp x0, mmu_cfg_params 23 add x0, x0, :lo12:mmu_cfg_params 24 25 /* (MAIRs are already set up) */ 26 27 /* TCR */ 28 ldr x2, [x0, #(MMU_CFG_TCR << 3)] 29 msr tcr_el2, x2 30 31 /* 32 * Ensure all translation table writes have drained into memory, the TLB 33 * invalidation is complete, and translation register writes are 34 * committed before enabling the MMU 35 */ 36 dsb ish 37 isb 38 39 /* Set and clear required fields of SCTLR */ 40 mrs x4, sctlr_el2 41 mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT 42 orr x4, x4, x5 43 44 /* Additionally, amend SCTLR fields based on flags */ 45 bic x5, x4, #SCTLR_C_BIT 46 tst x7, #DISABLE_DCACHE 47 csel x4, x5, x4, ne 48 49 msr sctlr_el2, x4 50 isb 51 52 ret 53endfunc enable_mpu_direct_el2 54