1#
2# Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/xlat_tables_v2/xlat_tables.mk
8include lib/libfdt/libfdt.mk
9include drivers/arm/gic/v2/gicv2.mk
10
11AW_PLAT			:=	plat/allwinner
12
13PLAT_INCLUDES		:=	-Iinclude/plat/arm/common/aarch64	\
14				-I${AW_PLAT}/common/include		\
15				-I${AW_PLAT}/${PLAT}/include
16
17PLAT_BL_COMMON_SOURCES	:=	drivers/ti/uart/${ARCH}/16550_console.S	\
18				${XLAT_TABLES_LIB_SRCS}			\
19				${AW_PLAT}/common/plat_helpers.S	\
20				${AW_PLAT}/common/sunxi_common.c
21
22BL31_SOURCES		+=	drivers/allwinner/axp/common.c		\
23				${GICV2_SOURCES}			\
24				drivers/delay_timer/delay_timer.c	\
25				drivers/delay_timer/generic_delay_timer.c \
26				lib/cpus/${ARCH}/cortex_a53.S		\
27				plat/common/plat_gicv2.c		\
28				plat/common/plat_psci_common.c		\
29				${AW_PLAT}/common/sunxi_bl31_setup.c	\
30				${AW_PLAT}/common/sunxi_pm.c		\
31				${AW_PLAT}/${PLAT}/sunxi_power.c	\
32				${AW_PLAT}/common/sunxi_security.c	\
33				${AW_PLAT}/common/sunxi_topology.c
34
35# By default, attempt to use SCPI to the ARISC management processor. If SCPI
36# is not enabled or SCP firmware is not loaded, fall back to a simpler native
37# implementation that does not support CPU or system suspend.
38#
39# If SCP firmware will always be present (or absent), the unused implementation
40# can be compiled out.
41SUNXI_PSCI_USE_NATIVE	?=	1
42SUNXI_PSCI_USE_SCPI	?=	1
43
44$(eval $(call assert_boolean,SUNXI_PSCI_USE_NATIVE))
45$(eval $(call assert_boolean,SUNXI_PSCI_USE_SCPI))
46$(eval $(call add_define,SUNXI_PSCI_USE_NATIVE))
47$(eval $(call add_define,SUNXI_PSCI_USE_SCPI))
48
49ifeq (${SUNXI_PSCI_USE_NATIVE}${SUNXI_PSCI_USE_SCPI},00)
50$(error "At least one of SCPI or native PSCI ops must be enabled")
51endif
52
53ifeq (${SUNXI_PSCI_USE_NATIVE},1)
54BL31_SOURCES		+=	${AW_PLAT}/common/sunxi_cpu_ops.c	\
55				${AW_PLAT}/common/sunxi_native_pm.c
56endif
57
58ifeq (${SUNXI_PSCI_USE_SCPI},1)
59BL31_SOURCES		+=	drivers/allwinner/sunxi_msgbox.c	\
60				drivers/arm/css/scpi/css_scpi.c		\
61				${AW_PLAT}/common/sunxi_scpi_pm.c
62endif
63
64# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
65COLD_BOOT_SINGLE_CPU		:=	1
66
67# Do not enable SPE (not supported on ARM v8.0).
68ENABLE_SPE_FOR_LOWER_ELS	:=	0
69
70# Do not enable SVE (not supported on ARM v8.0).
71ENABLE_SVE_FOR_NS		:=	0
72
73# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
74ERRATA_A53_835769		:=	1
75ERRATA_A53_843419		:=	1
76ERRATA_A53_855873		:=	1
77ERRATA_A53_1530924		:=	1
78
79# The traditional U-Boot load address is 160MB into DRAM.
80PRELOADED_BL33_BASE		?=	0x4a000000
81
82# The reset vector can be changed for each CPU.
83PROGRAMMABLE_RESET_ADDRESS	:=	1
84
85# Allow mapping read-only data as execute-never.
86SEPARATE_CODE_AND_RODATA	:=	1
87
88# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
89RESET_TO_BL31			:=	1
90
91# This platform is single-cluster and does not require coherency setup.
92WARMBOOT_ENABLE_DCACHE_EARLY	:=	1
93