1 /*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <libfdt.h>
10
11 #include <platform_def.h>
12
13 #include <arch.h>
14 #include <arch_helpers.h>
15 #include <common/debug.h>
16 #include <common/fdt_fixup.h>
17 #include <common/fdt_wrappers.h>
18 #include <drivers/arm/gicv2.h>
19 #include <drivers/console.h>
20 #include <drivers/generic_delay_timer.h>
21 #include <drivers/ti/uart/uart_16550.h>
22 #include <lib/mmio.h>
23 #include <plat/common/platform.h>
24
25 #include <sunxi_def.h>
26 #include <sunxi_mmap.h>
27 #include <sunxi_private.h>
28
29
30 static entry_point_info_t bl32_image_ep_info;
31 static entry_point_info_t bl33_image_ep_info;
32
33 static console_t console;
34
35 static const gicv2_driver_data_t sunxi_gic_data = {
36 .gicd_base = SUNXI_GICD_BASE,
37 .gicc_base = SUNXI_GICC_BASE,
38 };
39
40 /*
41 * Try to find a DTB loaded in memory by previous stages.
42 *
43 * At the moment we implement a heuristic to find the DTB attached to U-Boot:
44 * U-Boot appends its DTB to the end of the image. Assuming that BL33 is
45 * U-Boot, try to find the size of the U-Boot image to learn the DTB address.
46 * The generic ARMv8 U-Boot image contains the load address and its size
47 * as u64 variables at the beginning of the image. There might be padding
48 * or other headers before that data, so scan the first 2KB after the BL33
49 * entry point to find the load address, which should be followed by the
50 * size. Adding those together gives us the address of the DTB.
51 */
sunxi_find_dtb(void)52 static void *sunxi_find_dtb(void)
53 {
54 uint64_t *u_boot_base;
55 int i;
56
57 u_boot_base = (void *)SUNXI_BL33_VIRT_BASE;
58
59 for (i = 0; i < 2048 / sizeof(uint64_t); i++) {
60 uint32_t *dtb_base;
61
62 if (u_boot_base[i] != PRELOADED_BL33_BASE)
63 continue;
64
65 /* Does the suspected U-Boot size look anyhow reasonable? */
66 if (u_boot_base[i + 1] >= 256 * 1024 * 1024)
67 continue;
68
69 /* end of the image: base address + size */
70 dtb_base = (void *)((char *)u_boot_base + u_boot_base[i + 1]);
71
72 if (fdt_check_header(dtb_base) != 0)
73 continue;
74
75 return dtb_base;
76 }
77
78 return NULL;
79 }
80
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)81 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
82 u_register_t arg2, u_register_t arg3)
83 {
84 /* Initialize the debug console as soon as possible */
85 console_16550_register(SUNXI_UART0_BASE, SUNXI_UART0_CLK_IN_HZ,
86 SUNXI_UART0_BAUDRATE, &console);
87
88 #ifdef BL32_BASE
89 /* Populate entry point information for BL32 */
90 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
91 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
92 bl32_image_ep_info.pc = BL32_BASE;
93 #endif
94
95 /* Populate entry point information for BL33 */
96 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
97 /*
98 * Tell BL31 where the non-trusted software image
99 * is located and the entry state information
100 */
101 bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
102 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
103 DISABLE_ALL_EXCEPTIONS);
104 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
105 }
106
bl31_plat_arch_setup(void)107 void bl31_plat_arch_setup(void)
108 {
109 sunxi_configure_mmu_el3(0);
110 }
111
bl31_platform_setup(void)112 void bl31_platform_setup(void)
113 {
114 const char *soc_name;
115 uint16_t soc_id = sunxi_read_soc_id();
116 void *fdt;
117
118 switch (soc_id) {
119 case SUNXI_SOC_A64:
120 soc_name = "A64/H64/R18";
121 break;
122 case SUNXI_SOC_H5:
123 soc_name = "H5";
124 break;
125 case SUNXI_SOC_H6:
126 soc_name = "H6";
127 break;
128 case SUNXI_SOC_H616:
129 soc_name = "H616";
130 break;
131 case SUNXI_SOC_R329:
132 soc_name = "R329";
133 break;
134 default:
135 soc_name = "unknown";
136 break;
137 }
138 NOTICE("BL31: Detected Allwinner %s SoC (%04x)\n", soc_name, soc_id);
139
140 generic_delay_timer_init();
141
142 fdt = sunxi_find_dtb();
143 if (fdt) {
144 const char *model;
145 int length;
146
147 model = fdt_getprop(fdt, 0, "model", &length);
148 NOTICE("BL31: Found U-Boot DTB at %p, model: %s\n", fdt,
149 model ?: "unknown");
150 } else {
151 NOTICE("BL31: No DTB found.\n");
152 }
153
154 /* Configure the interrupt controller */
155 gicv2_driver_init(&sunxi_gic_data);
156 gicv2_distif_init();
157 gicv2_pcpu_distif_init();
158 gicv2_cpuif_enable();
159
160 sunxi_security_setup();
161
162 /*
163 * On the A64 U-Boot's SPL sets the bus clocks to some conservative
164 * values, to work around FEL mode instabilities with SRAM C accesses.
165 * FEL mode is gone when we reach ATF, so bring the AHB1 bus
166 * (the "main" bus) clock frequency back to the recommended 200MHz,
167 * for improved performance.
168 */
169 if (soc_id == SUNXI_SOC_A64)
170 mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x00003180);
171
172 /*
173 * U-Boot or the kernel don't setup AHB2, which leaves it at the
174 * AHB1 frequency (200 MHz, see above). However Allwinner recommends
175 * 300 MHz, for improved Ethernet and USB performance. Switch the
176 * clock to use "PLL_PERIPH0 / 2".
177 */
178 if (soc_id == SUNXI_SOC_A64 || soc_id == SUNXI_SOC_H5)
179 mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0x1);
180
181 sunxi_pmic_setup(soc_id, fdt);
182
183 sunxi_prepare_dtb(fdt);
184
185 INFO("BL31: Platform setup done\n");
186 }
187
bl31_plat_get_next_image_ep_info(uint32_t type)188 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
189 {
190 assert(sec_state_is_valid(type) != 0);
191
192 if (type == NON_SECURE)
193 return &bl33_image_ep_info;
194
195 if ((type == SECURE) && bl32_image_ep_info.pc)
196 return &bl32_image_ep_info;
197
198 return NULL;
199 }
200