1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SUNXI_MMAP_H 8 #define SUNXI_MMAP_H 9 10 /* Memory regions */ 11 #define SUNXI_ROM_BASE 0x00000000 12 #define SUNXI_ROM_SIZE 0x00010000 13 /* 14 * In fact all SRAM from 0x100000 is SRAM A2. However as it's too big for 15 * firmware, and the user manual gives a tip on a 2*64K/27*64K partition, 16 * only use the first 2*64K for firmwares now, with the SPL using the first 17 * 64K and BL3-1 using the second one. 18 * 19 * Only the used 2*64K SRAM is defined here, to prevent a gaint translation 20 * table to be generated. 21 */ 22 #define SUNXI_SRAM_BASE 0x00100000 23 #define SUNXI_SRAM_SIZE 0x00020000 24 #define SUNXI_SRAM_A1_BASE 0x00100000 25 #define SUNXI_SRAM_A1_SIZE 0x00010000 26 #define SUNXI_SRAM_A2_BASE 0x00110000 27 #define SUNXI_SRAM_A2_BL31_OFFSET 0x00000000 28 #define SUNXI_SRAM_A2_SIZE 0x00010000 29 #define SUNXI_DEV_BASE 0x01000000 30 #define SUNXI_DEV_SIZE 0x09000000 31 #define SUNXI_DRAM_BASE 0x40000000 32 #define SUNXI_DRAM_VIRT_BASE 0x0a000000 33 34 /* Memory-mapped devices */ 35 #define SUNXI_WDOG_BASE 0x020000a0 36 #define SUNXI_R_WDOG_BASE SUNXI_WDOG_BASE 37 #define SUNXI_PIO_BASE 0x02000400 38 #define SUNXI_SPC_BASE 0x02000800 39 #define SUNXI_CCU_BASE 0x02001000 40 #define SUNXI_UART0_BASE 0x02500000 41 #define SUNXI_SYSCON_BASE 0x03000000 42 #define SUNXI_DMA_BASE 0x03002000 43 #define SUNXI_SID_BASE 0x03006000 44 #define SUNXI_GICD_BASE 0x03021000 45 #define SUNXI_GICC_BASE 0x03022000 46 #define SUNXI_SPI0_BASE 0x04025000 47 #define SUNXI_R_CPUCFG_BASE 0x07000400 48 #define SUNXI_R_PRCM_BASE 0x07010000 49 #define SUNXI_R_PIO_BASE 0x07022000 50 #define SUNXI_R_UART_BASE 0x07080000 51 #define SUNXI_R_I2C_BASE 0x07081400 52 #define SUNXI_CPUCFG_BASE 0x08100000 53 #define SUNXI_C0_CPUXCFG_BASE 0x09010000 54 55 #endif /* SUNXI_MMAP_H */ 56