1 /*
2  * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef GXL_DEF_H
8 #define GXL_DEF_H
9 
10 #include <lib/utils_def.h>
11 
12 /*******************************************************************************
13  * System oscillator
14  ******************************************************************************/
15 #define AML_OSC24M_CLK_IN_HZ			ULL(24000000) /* 24 MHz */
16 
17 /*******************************************************************************
18  * Memory regions
19  ******************************************************************************/
20 #define AML_NSDRAM0_BASE			UL(0x01000000)
21 #define AML_NSDRAM0_SIZE			UL(0x0F000000)
22 
23 #define AML_NSDRAM1_BASE			UL(0x10000000)
24 #define AML_NSDRAM1_SIZE			UL(0x00100000)
25 
26 #define BL31_BASE				UL(0x05100000)
27 #define BL31_SIZE				UL(0x000C0000)
28 #define BL31_LIMIT				(BL31_BASE + BL31_SIZE)
29 
30 /* Shared memory used for SMC services */
31 #define AML_SHARE_MEM_INPUT_BASE		UL(0x050FE000)
32 #define AML_SHARE_MEM_OUTPUT_BASE		UL(0x050FF000)
33 
34 #define AML_SEC_DEVICE0_BASE			UL(0xC0000000)
35 #define AML_SEC_DEVICE0_SIZE			UL(0x09000000)
36 
37 #define AML_SEC_DEVICE1_BASE			UL(0xD0040000)
38 #define AML_SEC_DEVICE1_SIZE			UL(0x00008000)
39 
40 #define AML_TZRAM_BASE				UL(0xD9000000)
41 #define AML_TZRAM_SIZE				UL(0x00014000)
42 /* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
43 
44 /* Mailboxes */
45 #define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD	UL(0xD9013800)
46 #define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD	UL(0xD9013A00)
47 #define AML_PSCI_MAILBOX_BASE			UL(0xD9013F00)
48 
49 // * [	 1K]	0xD901_3800 - 0xD901_3BFF	Secure Mailbox (3)
50 // * [	 1K]	0xD901_3400 - 0xD901_37FF	High Mailbox (2) *
51 // * [	 1K]	0xD901_3000 - 0xD901_33FF	High Mailbox (1) *
52 
53 #define AML_TZROM_BASE				UL(0xD9040000)
54 #define AML_TZROM_SIZE				UL(0x00010000)
55 
56 #define AML_SEC_DEVICE2_BASE			UL(0xDA000000)
57 #define AML_SEC_DEVICE2_SIZE			UL(0x00200000)
58 
59 #define AML_SEC_DEVICE3_BASE			UL(0xDA800000)
60 #define AML_SEC_DEVICE3_SIZE			UL(0x00200000)
61 
62 /*******************************************************************************
63  * GIC-400 and interrupt handling related constants
64  ******************************************************************************/
65 #define AML_GICD_BASE				UL(0xC4301000)
66 #define AML_GICC_BASE				UL(0xC4302000)
67 
68 #define IRQ_SEC_PHY_TIMER			29
69 
70 #define IRQ_SEC_SGI_0				8
71 #define IRQ_SEC_SGI_1				9
72 #define IRQ_SEC_SGI_2				10
73 #define IRQ_SEC_SGI_3				11
74 #define IRQ_SEC_SGI_4				12
75 #define IRQ_SEC_SGI_5				13
76 #define IRQ_SEC_SGI_6				14
77 #define IRQ_SEC_SGI_7				15
78 
79 /*******************************************************************************
80  * UART definitions
81  ******************************************************************************/
82 #define AML_UART0_AO_BASE			UL(0xC81004C0)
83 #define AML_UART0_AO_CLK_IN_HZ			AML_OSC24M_CLK_IN_HZ
84 #define AML_UART_BAUDRATE			U(115200)
85 
86 /*******************************************************************************
87  * Memory-mapped I/O Registers
88  ******************************************************************************/
89 #define AML_AO_TIMESTAMP_CNTL			UL(0xC81000B4)
90 
91 #define AML_SYS_CPU_CFG7			UL(0xC8834664)
92 
93 #define AML_AO_RTI_STATUS_REG3			UL(0xDA10001C)
94 #define AML_AO_RTI_SCP_STAT			UL(0xDA10023C)
95 #define AML_AO_RTI_SCP_READY_OFF		U(0x14)
96 #define AML_A0_RTI_SCP_READY_MASK		U(3)
97 #define AML_AO_RTI_SCP_IS_READY(v)		\
98 	((((v) >> AML_AO_RTI_SCP_READY_OFF) & \
99 	  AML_A0_RTI_SCP_READY_MASK) == AML_A0_RTI_SCP_READY_MASK)
100 
101 #define AML_HIU_MAILBOX_SET_0			UL(0xDA83C404)
102 #define AML_HIU_MAILBOX_STAT_0			UL(0xDA83C408)
103 #define AML_HIU_MAILBOX_CLR_0			UL(0xDA83C40C)
104 #define AML_HIU_MAILBOX_SET_3			UL(0xDA83C428)
105 #define AML_HIU_MAILBOX_STAT_3			UL(0xDA83C42C)
106 #define AML_HIU_MAILBOX_CLR_3			UL(0xDA83C430)
107 
108 #define AML_SHA_DMA_BASE			UL(0xC883E000)
109 #define AML_SHA_DMA_DESC			(AML_SHA_DMA_BASE + 0x08)
110 #define AML_SHA_DMA_STATUS			(AML_SHA_DMA_BASE + 0x18)
111 
112 /*******************************************************************************
113  * System Monitor Call IDs and arguments
114  ******************************************************************************/
115 #define AML_SM_GET_SHARE_MEM_INPUT_BASE		U(0x82000020)
116 #define AML_SM_GET_SHARE_MEM_OUTPUT_BASE	U(0x82000021)
117 
118 #define AML_SM_EFUSE_READ			U(0x82000030)
119 #define AML_SM_EFUSE_USER_MAX			U(0x82000033)
120 
121 #define AML_SM_JTAG_ON				U(0x82000040)
122 #define AML_SM_JTAG_OFF				U(0x82000041)
123 #define AML_SM_GET_CHIP_ID			U(0x82000044)
124 
125 #define AML_JTAG_STATE_ON			U(0)
126 #define AML_JTAG_STATE_OFF			U(1)
127 
128 #define AML_JTAG_M3_AO				U(0)
129 #define AML_JTAG_M3_EE				U(1)
130 #define AML_JTAG_A53_AO				U(2)
131 #define AML_JTAG_A53_EE				U(3)
132 
133 #endif /* GXL_DEF_H */
134