1 /*
2  * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <arch_helpers.h>
8 #include <common/debug.h>
9 #include <lib/spinlock.h>
10 
11 #include "fpga_private.h"
12 #include <plat/common/platform.h>
13 #include <platform_def.h>
14 
15 unsigned char fpga_power_domain_tree_desc[FPGA_MAX_CLUSTER_COUNT + 2];
16 unsigned char fpga_valid_mpids[PLATFORM_CORE_COUNT];
17 
plat_get_power_domain_tree_desc(void)18 const unsigned char *plat_get_power_domain_tree_desc(void)
19 {
20 	unsigned int i;
21 
22 	/*
23 	* The highest level is the system level. The next level is constituted
24 	* by clusters and then cores in clusters.
25 	*
26 	* This description of the power domain topology is aligned with the CPU
27 	* indices returned by the plat_core_pos_by_mpidr() and plat_my_core_pos()
28 	* APIs.
29 	*
30 	* A description of the topology tree can be found at
31 	* https://trustedfirmware-a.readthedocs.io/en/latest/design/psci-pd-tree.html#design
32 	*/
33 
34 	if (fpga_power_domain_tree_desc[0] == 0U) {
35 		/*
36 		 * As fpga_power_domain_tree_desc[0] == 0, assume that the
37 		 * Power Domain Topology Tree has not been initialized, so
38 		 * perform the initialization here.
39 		 */
40 
41 		fpga_power_domain_tree_desc[0] = 1U;
42 		fpga_power_domain_tree_desc[1] = FPGA_MAX_CLUSTER_COUNT;
43 
44 		for (i = 0U; i < FPGA_MAX_CLUSTER_COUNT; i++) {
45 			fpga_power_domain_tree_desc[2 + i] =
46 				(FPGA_MAX_CPUS_PER_CLUSTER *
47 				 FPGA_MAX_PE_PER_CPU);
48 		}
49 	}
50 
51 	return fpga_power_domain_tree_desc;
52 }
53 
plat_core_pos_by_mpidr(u_register_t mpidr)54 int plat_core_pos_by_mpidr(u_register_t mpidr)
55 {
56 	unsigned int core_pos;
57 
58 	mpidr &= (MPID_MASK & ~(MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT));
59 	mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
60 
61 	if ((MPIDR_AFFLVL2_VAL(mpidr) >= FPGA_MAX_CLUSTER_COUNT) ||
62 	    (MPIDR_AFFLVL1_VAL(mpidr) >= FPGA_MAX_CPUS_PER_CLUSTER) ||
63 	    (MPIDR_AFFLVL0_VAL(mpidr) >= FPGA_MAX_PE_PER_CPU)) {
64 		ERROR ("Invalid mpidr: 0x%08x\n", (uint32_t)mpidr);
65 		panic();
66 	}
67 
68 	/* Calculate the core position, based on the maximum topology. */
69 	core_pos = plat_fpga_calc_core_pos(mpidr);
70 
71 	/* Check whether this core is actually present. */
72 	if (fpga_valid_mpids[core_pos] != VALID_MPID) {
73 		return -1;
74 	}
75 
76 	return core_pos;
77 }
78