1 /* 2 * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 #include <plat/arm/board/common/v2m_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/arm/common/smccc_def.h> 16 #include <plat/common/common_def.h> 17 #include <plat/arm/soc/common/soc_css_def.h> 18 19 #define ARM_ROTPK_HEADER_LEN 19 20 #define ARM_ROTPK_HASH_LEN 32 21 22 /* Special value used to verify platform parameters from BL2 to BL31 */ 23 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 24 25 /* PL011 UART related constants */ 26 #ifdef V2M_IOFPGA_UART0_CLK_IN_HZ 27 #undef V2M_IOFPGA_UART0_CLK_IN_HZ 28 #endif 29 30 #ifdef V2M_IOFPGA_UART1_CLK_IN_HZ 31 #undef V2M_IOFPGA_UART1_CLK_IN_HZ 32 #endif 33 34 #define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000 35 #define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000 36 37 /* Core/Cluster/Thread counts for diphda */ 38 #define DIPHDA_CLUSTER_COUNT U(1) 39 #define DIPHDA_MAX_CPUS_PER_CLUSTER U(4) 40 #define DIPHDA_MAX_PE_PER_CPU U(1) 41 #define DIPHDA_PRIMARY_CPU U(0) 42 43 #define PLAT_ARM_CLUSTER_COUNT DIPHDA_CLUSTER_COUNT 44 45 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ 46 DIPHDA_MAX_CPUS_PER_CLUSTER * \ 47 DIPHDA_MAX_PE_PER_CPU) 48 49 /* UART related constants */ 50 #define PLAT_ARM_BOOT_UART_BASE 0x1a510000 51 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 52 #define PLAT_ARM_RUN_UART_BASE 0x1a520000 53 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 54 #define ARM_CONSOLE_BAUDRATE 115200 55 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 56 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 57 58 /* Memory related constants */ 59 60 /* SRAM (CVM) memory layout 61 * 62 * <ARM_TRUSTED_SRAM_BASE> 63 * 64 * partition size: sizeof(meminfo_t) = 16 bytes 65 * 66 * content: memory info area used by the next BL 67 * 68 * <ARM_FW_CONFIG_BASE> 69 * 70 * partition size: 4080 bytes 71 * 72 * <ARM_BL2_MEM_DESC_BASE> 73 * 74 * partition size: 4 KB 75 * 76 * content: 77 * 78 * Area where BL2 copies the images descriptors 79 * 80 * <ARM_BL_RAM_BASE> = <BL32_BASE> 81 * 82 * partition size: 688 KB 83 * 84 * content: 85 * 86 * BL32 (optee-os) 87 * 88 * <DIPHDA_TOS_FW_CONFIG_BASE> = 0x20ae000 89 * 90 * partition size: 8 KB 91 * 92 * content: 93 * 94 * BL32 config (TOS_FW_CONFIG) 95 * 96 * <BL31_BASE> 97 * 98 * partition size: 140 KB 99 * 100 * content: 101 * 102 * BL31 103 * 104 * <BL2_SIGNATURE_BASE> 105 * 106 * partition size: 4 KB 107 * 108 * content: 109 * 110 * MCUBOOT data needed to verify TF-A BL2 111 * 112 * <BL2_BASE> 113 * 114 * partition size: 176 KB 115 * 116 * content: 117 * 118 * BL2 119 * 120 * <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB 121 * 122 * partition size: 3 MB 123 * 124 * content: 125 * 126 * BL33 (u-boot) 127 */ 128 129 /* DDR memory */ 130 #define ARM_DRAM1_BASE UL(0x80000000) 131 #define ARM_DRAM1_SIZE UL(0x80000000) 132 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 133 ARM_DRAM1_SIZE - 1) 134 135 /* DRAM1 and DRAM2 are the same for diphda */ 136 #define ARM_DRAM2_BASE ARM_DRAM1_BASE 137 #define ARM_DRAM2_SIZE ARM_DRAM1_SIZE 138 #define ARM_DRAM2_END ARM_DRAM1_END 139 140 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 141 #define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE 142 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 143 ARM_NS_DRAM1_SIZE - 1) 144 145 /* The first 8 KB of Trusted SRAM are used as shared memory */ 146 #define ARM_TRUSTED_SRAM_BASE UL(0x02000000) 147 #define ARM_SHARED_RAM_SIZE UL(0x00002000) /* 8 KB */ 148 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 149 150 /* The remaining Trusted SRAM is used to load the BL images */ 151 152 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00100000) /* 1 MB */ 153 154 #define PLAT_ARM_MAX_BL2_SIZE UL(0x0002d000) /* 180 KB */ 155 156 #define PLAT_ARM_MAX_BL31_SIZE UL(0x00023000) /* 140 KB */ 157 158 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 159 ARM_SHARED_RAM_SIZE) 160 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 161 ARM_SHARED_RAM_SIZE) 162 163 #define BL2_SIGNATURE_SIZE UL(0x00001000) /* 4 KB */ 164 #define BL2_SIGNATURE_BASE (BL2_LIMIT - \ 165 PLAT_ARM_MAX_BL2_SIZE) 166 #define BL2_BASE (BL2_LIMIT - \ 167 PLAT_ARM_MAX_BL2_SIZE + \ 168 BL2_SIGNATURE_SIZE) 169 #define BL2_LIMIT (ARM_BL_RAM_BASE + \ 170 ARM_BL_RAM_SIZE) 171 172 #define BL31_BASE (BL2_SIGNATURE_BASE - \ 173 PLAT_ARM_MAX_BL31_SIZE) 174 #define BL31_LIMIT BL2_SIGNATURE_BASE 175 176 #define DIPHDA_TOS_FW_CONFIG_BASE (BL31_BASE - \ 177 DIPHDA_TOS_FW_CONFIG_SIZE) 178 #define DIPHDA_TOS_FW_CONFIG_SIZE UL(0x00002000) /* 8 KB */ 179 #define DIPHDA_TOS_FW_CONFIG_LIMIT BL31_BASE 180 181 #define BL32_BASE ARM_BL_RAM_BASE 182 #define PLAT_ARM_MAX_BL32_SIZE (DIPHDA_TOS_FW_CONFIG_BASE - \ 183 BL32_BASE) /* 688 KB */ 184 #define BL32_LIMIT (BL32_BASE + \ 185 PLAT_ARM_MAX_BL32_SIZE) 186 187 /* SPD_spmd settings */ 188 189 #define PLAT_ARM_SPMC_BASE BL32_BASE 190 #define PLAT_ARM_SPMC_SIZE PLAT_ARM_MAX_BL32_SIZE 191 192 /* NS memory */ 193 194 /* The last 3 MB of the SRAM is allocated to the non secure area */ 195 #define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + \ 196 PLAT_ARM_TRUSTED_SRAM_SIZE) 197 #define ARM_NS_SHARED_RAM_SIZE UL(0x00300000) /* 3 MB */ 198 199 /* end of the definition of SRAM memory layout */ 200 201 /* NOR Flash */ 202 203 #define PLAT_ARM_FIP_BASE UL(0x08131000) 204 #define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */ 205 206 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 207 #define PLAT_ARM_NVM_SIZE UL(0x02000000) /* 32 MB */ 208 209 #define PLAT_ARM_FLASH_IMAGE_BASE PLAT_ARM_FIP_BASE 210 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE 211 212 /* 213 * Some data must be aligned on the biggest cache line size in the platform. 214 * This is known only to the platform as it might have a combination of 215 * integrated and external caches. 216 */ 217 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 218 #define ARM_CACHE_WRITEBACK_SHIFT 6 219 220 /* 221 * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo. 222 * FW_CONFIG is intended to host the device tree. Currently, This area is not 223 * used because diphda platform doesn't use a device tree at TF-A level. 224 */ 225 #define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE \ 226 + sizeof(meminfo_t)) 227 #define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE \ 228 + (ARM_SHARED_RAM_SIZE >> 1)) 229 230 /* 231 * Boot parameters passed from BL2 to BL31/BL32 are stored here 232 */ 233 #define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT 234 #define ARM_BL2_MEM_DESC_LIMIT ARM_BL_RAM_BASE 235 236 /* 237 * The max number of regions like RO(code), coherent and data required by 238 * different BL stages which need to be mapped in the MMU. 239 */ 240 #define ARM_BL_REGIONS 3 241 #define PLAT_ARM_MMAP_ENTRIES 8 242 #define MAX_XLAT_TABLES 5 243 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 244 ARM_BL_REGIONS) 245 #define MAX_IO_DEVICES 2 246 #define MAX_IO_HANDLES 3 247 #define MAX_IO_BLOCK_DEVICES 1 248 249 /* GIC related constants */ 250 #define PLAT_ARM_GICD_BASE 0x1C010000 251 #define PLAT_ARM_GICC_BASE 0x1C02F000 252 253 /* MHUv2 Secure Channel receiver and sender */ 254 #define PLAT_SDK700_MHU0_SEND 0x1B800000 255 #define PLAT_SDK700_MHU0_RECV 0x1B810000 256 257 /* Timer/watchdog related constants */ 258 #define ARM_SYS_CNTCTL_BASE UL(0x1a200000) 259 #define ARM_SYS_CNTREAD_BASE UL(0x1a210000) 260 #define ARM_SYS_TIMCTL_BASE UL(0x1a220000) 261 262 #define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ 263 264 #define DIPHDA_IRQ_TZ_WDOG 32 265 #define DIPHDA_IRQ_SEC_SYS_TIMER 34 266 267 #define PLAT_MAX_PWR_LVL 2 268 /* 269 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 270 * power levels have a 1:1 mapping with the MPIDR affinity levels. 271 */ 272 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 273 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 274 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 275 276 /* 277 * Macros for local power states in ARM platforms encoded by State-ID field 278 * within the power-state parameter. 279 */ 280 /* Local power state for power domains in Run state. */ 281 #define ARM_LOCAL_STATE_RUN U(0) 282 /* Local power state for retention. Valid only for CPU power domains */ 283 #define ARM_LOCAL_STATE_RET U(1) 284 /* Local power state for OFF/power-down. Valid for CPU and cluster 285 * power domains 286 */ 287 #define ARM_LOCAL_STATE_OFF U(2) 288 289 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 290 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 291 292 #define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE) 293 294 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 295 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 296 297 /* 298 * This macro defines the deepest retention state possible. A higher state 299 * ID will represent an invalid or a power down state. 300 */ 301 #define PLAT_MAX_RET_STATE 1 302 303 /* 304 * This macro defines the deepest power down states possible. Any state ID 305 * higher than this is invalid. 306 */ 307 #define PLAT_MAX_OFF_STATE 2 308 309 #define PLATFORM_STACK_SIZE UL(0x440) 310 311 #define DIPHDA_EXTERNAL_FLASH MAP_REGION_FLAT( \ 312 PLAT_ARM_NVM_BASE, \ 313 PLAT_ARM_NVM_SIZE, \ 314 MT_DEVICE | MT_RO | MT_SECURE) 315 316 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 317 ARM_SHARED_RAM_BASE, \ 318 ARM_SHARED_RAM_SIZE, \ 319 MT_MEMORY | MT_RW | MT_SECURE) 320 321 #define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \ 322 ARM_NS_SHARED_RAM_BASE, \ 323 ARM_NS_SHARED_RAM_SIZE, \ 324 MT_MEMORY | MT_RW | MT_NS) 325 326 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 327 ARM_NS_DRAM1_BASE, \ 328 ARM_NS_DRAM1_SIZE, \ 329 MT_MEMORY | MT_RW | MT_NS) 330 331 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 332 BL_CODE_BASE, \ 333 BL_CODE_END \ 334 - BL_CODE_BASE, \ 335 MT_CODE | MT_SECURE), \ 336 MAP_REGION_FLAT( \ 337 BL_RO_DATA_BASE, \ 338 BL_RO_DATA_END \ 339 - BL_RO_DATA_BASE, \ 340 MT_RO_DATA | MT_SECURE) 341 #if USE_COHERENT_MEM 342 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 343 BL_COHERENT_RAM_BASE, \ 344 BL_COHERENT_RAM_END \ 345 - BL_COHERENT_RAM_BASE, \ 346 MT_DEVICE | MT_RW | MT_SECURE) 347 #endif 348 349 /* 350 * Map the region for the optional device tree configuration with read and 351 * write permissions 352 */ 353 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \ 354 ARM_FW_CONFIG_BASE, \ 355 (ARM_FW_CONFIG_LIMIT- \ 356 ARM_FW_CONFIG_BASE), \ 357 MT_MEMORY | MT_RW | MT_SECURE) 358 359 #define DIPHDA_DEVICE_BASE (0x1A000000) 360 #define DIPHDA_DEVICE_SIZE (0x26000000) 361 #define DIPHDA_MAP_DEVICE MAP_REGION_FLAT( \ 362 DIPHDA_DEVICE_BASE, \ 363 DIPHDA_DEVICE_SIZE, \ 364 MT_DEVICE | MT_RW | MT_SECURE) 365 366 #define ARM_IRQ_SEC_PHY_TIMER 29 367 368 #define ARM_IRQ_SEC_SGI_0 8 369 #define ARM_IRQ_SEC_SGI_1 9 370 #define ARM_IRQ_SEC_SGI_2 10 371 #define ARM_IRQ_SEC_SGI_3 11 372 #define ARM_IRQ_SEC_SGI_4 12 373 #define ARM_IRQ_SEC_SGI_5 13 374 #define ARM_IRQ_SEC_SGI_6 14 375 #define ARM_IRQ_SEC_SGI_7 15 376 377 /* 378 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 379 * terminology. On a GICv2 system or mode, the lists will be merged and treated 380 * as Group 0 interrupts. 381 */ 382 #define ARM_G1S_IRQ_PROPS(grp) \ 383 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 384 (grp), GIC_INTR_CFG_LEVEL), \ 385 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 386 (grp), GIC_INTR_CFG_EDGE), \ 387 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 388 (grp), GIC_INTR_CFG_EDGE), \ 389 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 390 (grp), GIC_INTR_CFG_EDGE), \ 391 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 392 (grp), GIC_INTR_CFG_EDGE), \ 393 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 394 (grp), GIC_INTR_CFG_EDGE), \ 395 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 396 (grp), GIC_INTR_CFG_EDGE) 397 398 #define ARM_G0_IRQ_PROPS(grp) \ 399 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 400 GIC_INTR_CFG_EDGE) 401 402 /* 403 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 404 * terminology. On a GICv2 system or mode, the lists will be merged and treated 405 * as Group 0 interrupts. 406 */ 407 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 408 ARM_G1S_IRQ_PROPS(grp), \ 409 INTR_PROP_DESC(DIPHDA_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \ 410 (grp), GIC_INTR_CFG_LEVEL), \ 411 INTR_PROP_DESC(DIPHDA_IRQ_SEC_SYS_TIMER, \ 412 GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) 413 414 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 415 416 #endif /* PLATFORM_DEF_H */ 417