1 /*
2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch.h>
10 #include <drivers/arm/fvp/fvp_pwrc.h>
11 #include <fconf_hw_config_getter.h>
12 #include <lib/cassert.h>
13 #include <plat/arm/common/arm_config.h>
14 #include <plat/arm/common/plat_arm.h>
15 #include <plat/common/platform.h>
16
17 #include <platform_def.h>
18
19 /* The FVP power domain tree descriptor */
20 static unsigned char fvp_power_domain_tree_desc[FVP_CLUSTER_COUNT + 2];
21
22
23 CASSERT(((FVP_CLUSTER_COUNT > 0) && (FVP_CLUSTER_COUNT <= 256)),
24 assert_invalid_fvp_cluster_count);
25
26 /*******************************************************************************
27 * This function dynamically constructs the topology according to cpu-map node
28 * in HW_CONFIG dtb and returns it.
29 ******************************************************************************/
plat_get_power_domain_tree_desc(void)30 const unsigned char *plat_get_power_domain_tree_desc(void)
31 {
32 unsigned int i;
33 uint32_t cluster_count, cpus_per_cluster;
34
35 /*
36 * fconf APIs are not supported for RESET_TO_SP_MIN, RESET_TO_BL31 and
37 * BL2_AT_EL3 systems.
38 */
39 #if RESET_TO_SP_MIN || RESET_TO_BL31 || BL2_AT_EL3
40 cluster_count = FVP_CLUSTER_COUNT;
41 cpus_per_cluster = FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU;
42 #else
43 cluster_count = FCONF_GET_PROPERTY(hw_config, topology, plat_cluster_count);
44 cpus_per_cluster = FCONF_GET_PROPERTY(hw_config, topology, cluster_cpu_count);
45 /* Several FVP Models use the same blanket dts. Ex: FVP_Base_Cortex-A65x4
46 * and FVP_Base_Cortex-A65AEx8 both use same dts but have different number of
47 * CPUs in the cluster, as reflected by build flags FVP_MAX_CPUS_PER_CLUSTER.
48 * Take the minimum of two to ensure PSCI functions do not exceed the size of
49 * the PSCI data structures allocated at build time.
50 */
51 cpus_per_cluster = MIN(cpus_per_cluster,
52 (uint32_t)(FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU));
53
54 #endif
55
56 assert(cluster_count > 0U);
57 assert(cpus_per_cluster > 0U);
58
59 /*
60 * The highest level is the system level. The next level is constituted
61 * by clusters and then cores in clusters.
62 */
63 fvp_power_domain_tree_desc[0] = 1;
64 fvp_power_domain_tree_desc[1] = (unsigned char)cluster_count;
65
66 for (i = 0; i < cluster_count; i++)
67 fvp_power_domain_tree_desc[i + 2] = (unsigned char)cpus_per_cluster;
68
69 return fvp_power_domain_tree_desc;
70 }
71
72 /*******************************************************************************
73 * This function returns the core count within the cluster corresponding to
74 * `mpidr`.
75 ******************************************************************************/
plat_arm_get_cluster_core_count(u_register_t mpidr)76 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
77 {
78 return FVP_MAX_CPUS_PER_CLUSTER;
79 }
80
81 /*******************************************************************************
82 * This function implements a part of the critical interface between the psci
83 * generic layer and the platform that allows the former to query the platform
84 * to convert an MPIDR to a unique linear index. An error code (-1) is returned
85 * in case the MPIDR is invalid.
86 ******************************************************************************/
plat_core_pos_by_mpidr(u_register_t mpidr)87 int plat_core_pos_by_mpidr(u_register_t mpidr)
88 {
89 unsigned int clus_id, cpu_id, thread_id;
90
91 /* Validate affinity fields */
92 if ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) {
93 thread_id = MPIDR_AFFLVL0_VAL(mpidr);
94 cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
95 clus_id = MPIDR_AFFLVL2_VAL(mpidr);
96 } else {
97 thread_id = 0;
98 cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
99 clus_id = MPIDR_AFFLVL1_VAL(mpidr);
100 }
101
102 if (clus_id >= FVP_CLUSTER_COUNT)
103 return -1;
104 if (cpu_id >= FVP_MAX_CPUS_PER_CLUSTER)
105 return -1;
106 if (thread_id >= FVP_MAX_PE_PER_CPU)
107 return -1;
108
109 if (fvp_pwrc_read_psysr(mpidr) == PSYSR_INVALID)
110 return -1;
111
112 /*
113 * Core position calculation for FVP platform depends on the MT bit in
114 * MPIDR. This function cannot assume that the supplied MPIDR has the MT
115 * bit set even if the implementation has. For example, PSCI clients
116 * might supply MPIDR values without the MT bit set. Therefore, we
117 * inject the current PE's MT bit so as to get the calculation correct.
118 * This of course assumes that none or all CPUs on the platform has MT
119 * bit set.
120 */
121 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
122 return (int) plat_arm_calc_core_pos(mpidr);
123 }
124