1# 2# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Include GICv2 driver files 10include drivers/arm/gic/v2/gicv2.mk 11 12JUNO_GIC_SOURCES := ${GICV2_SOURCES} \ 13 plat/common/plat_gicv2.c \ 14 plat/arm/common/arm_gicv2.c 15 16JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ 17 plat/arm/common/arm_cci.c 18 19JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 20 plat/arm/board/juno/juno_security.c \ 21 plat/arm/board/juno/juno_trng.c \ 22 plat/arm/common/arm_tzc400.c 23 24ifneq (${ENABLE_STACK_PROTECTOR}, 0) 25JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c 26endif 27 28# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 29# SCP during power management operations and for SCP RAM Firmware transfer. 30CSS_USE_SCMI_SDS_DRIVER := 1 31 32PLAT_INCLUDES := -Iplat/arm/board/juno/include 33 34PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S \ 35 plat/arm/board/juno/juno_common.c 36 37# Flag to enable support for AArch32 state on JUNO 38JUNO_AARCH32_EL3_RUNTIME := 0 39$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME)) 40$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME)) 41 42# Flag to enable support for TZMP1 on JUNO 43JUNO_TZMP1 := 0 44$(eval $(call assert_boolean,JUNO_TZMP1)) 45ifeq (${JUNO_TZMP1}, 1) 46$(eval $(call add_define,JUNO_TZMP1)) 47endif 48 49TRNG_SUPPORT := 1 50 51ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 52# Include BL32 in FIP 53NEED_BL32 := yes 54# BL31 is not required 55override BL31_SOURCES = 56 57# The BL32 needs to be built separately invoking the AARCH32 compiler and 58# be specifed via `BL32` build option. 59 ifneq (${ARCH}, aarch32) 60 override BL32_SOURCES = 61 endif 62endif 63 64ifeq (${ARCH},aarch64) 65BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 66 lib/cpus/aarch64/cortex_a57.S \ 67 lib/cpus/aarch64/cortex_a72.S \ 68 plat/arm/board/juno/juno_err.c \ 69 plat/arm/board/juno/juno_bl1_setup.c \ 70 drivers/arm/sp805/sp805.c \ 71 ${JUNO_INTERCONNECT_SOURCES} \ 72 ${JUNO_SECURITY_SOURCES} 73 74BL2_SOURCES += drivers/arm/sp805/sp805.c \ 75 lib/utils/mem_region.c \ 76 plat/arm/board/juno/juno_err.c \ 77 plat/arm/board/juno/juno_bl2_setup.c \ 78 plat/arm/common/arm_nor_psci_mem_protect.c \ 79 ${JUNO_SECURITY_SOURCES} 80 81BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} 82 83BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ 84 lib/cpus/aarch64/cortex_a53.S \ 85 lib/cpus/aarch64/cortex_a57.S \ 86 lib/cpus/aarch64/cortex_a72.S \ 87 lib/utils/mem_region.c \ 88 lib/fconf/fconf.c \ 89 lib/fconf/fconf_dyn_cfg_getter.c \ 90 plat/arm/board/juno/juno_bl31_setup.c \ 91 plat/arm/board/juno/juno_pm.c \ 92 plat/arm/board/juno/juno_topology.c \ 93 plat/arm/common/arm_nor_psci_mem_protect.c \ 94 ${JUNO_GIC_SOURCES} \ 95 ${JUNO_INTERCONNECT_SOURCES} \ 96 ${JUNO_SECURITY_SOURCES} 97 98BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 99 100ifeq (${CSS_USE_SCMI_SDS_DRIVER},1) 101BL1_SOURCES += drivers/arm/css/sds/sds.c 102endif 103 104ifeq (${TRUSTED_BOARD_BOOT}, 1) 105BL1_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 106BL2_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 107endif 108 109endif 110 111ifneq (${RESET_TO_BL31},0) 112 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \ 113 Please set RESET_TO_BL31 to 0.") 114endif 115 116ifeq ($(USE_ROMLIB),1) 117all : bl1_romlib.bin 118endif 119 120bl1_romlib.bin : $(BUILD_PLAT)/bl1.bin romlib.bin 121 @echo "Building combined BL1 and ROMLIB binary for Juno $@" 122 ./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT) 123 124# Errata workarounds for Cortex-A53: 125ERRATA_A53_819472 := 1 126ERRATA_A53_824069 := 1 127ERRATA_A53_826319 := 1 128ERRATA_A53_827319 := 1 129ERRATA_A53_835769 := 1 130ERRATA_A53_836870 := 1 131ERRATA_A53_843419 := 1 132ERRATA_A53_855873 := 1 133 134# Errata workarounds for Cortex-A57: 135ERRATA_A57_806969 := 0 136ERRATA_A57_813419 := 1 137ERRATA_A57_813420 := 1 138ERRATA_A57_814670 := 1 139ERRATA_A57_817169 := 1 140ERRATA_A57_826974 := 1 141ERRATA_A57_826977 := 1 142ERRATA_A57_828024 := 1 143ERRATA_A57_829520 := 1 144ERRATA_A57_833471 := 1 145ERRATA_A57_859972 := 0 146 147# Errata workarounds for Cortex-A72: 148ERRATA_A72_859971 := 0 149 150# Enable option to skip L1 data cache flush during the Cortex-A57 cluster 151# power down sequence 152SKIP_A57_L1_FLUSH_PWR_DWN := 1 153 154# Do not enable SVE 155ENABLE_SVE_FOR_NS := 0 156 157# Enable the dynamic translation tables library. 158ifeq (${ARCH},aarch32) 159 ifeq (${RESET_TO_SP_MIN},1) 160 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 161 endif 162else 163 ifeq (${RESET_TO_BL31},1) 164 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 165 endif 166endif 167 168ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 169 ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 170 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 171 else 172 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 173 endif 174endif 175 176BL1_CPPFLAGS += -march=armv8-a+crc 177BL2_CPPFLAGS += -march=armv8-a+crc 178BL2U_CPPFLAGS += -march=armv8-a+crc 179BL31_CPPFLAGS += -march=armv8-a+crc 180BL32_CPPFLAGS += -march=armv8-a+crc 181 182# Add the FDT_SOURCES and options for Dynamic Config 183FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_fw_config.dts \ 184 plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts \ 185 fdts/${PLAT}.dts 186 187FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 188TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 189HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb 190 191# Add the FW_CONFIG to FIP and specify the same to certtool 192$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 193# Add the TB_FW_CONFIG to FIP and specify the same to certtool 194$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 195# Add the HW_CONFIG to FIP and specify the same to certtool 196$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG})) 197 198include plat/arm/board/common/board_common.mk 199include plat/arm/common/arm_common.mk 200include plat/arm/soc/common/soc_css.mk 201include plat/arm/css/common/css_common.mk 202