1 /* 2 * Copyright (c) 2020, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <plat/arm/board/common/v2m_def.h> 11 #include <plat/arm/common/arm_def.h> 12 #include <plat/arm/css/common/css_def.h> 13 14 /* UART related constants */ 15 #define PLAT_ARM_BOOT_UART_BASE ULL(0x2A400000) 16 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ U(50000000) 17 18 #define PLAT_ARM_RUN_UART_BASE ULL(0x2A410000) 19 #define PLAT_ARM_RUN_UART_CLK_IN_HZ U(50000000) 20 21 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 22 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 23 24 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 25 #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000) 26 27 /* 28 * To access the complete DDR memory along with remote chip's DDR memory, 29 * which is at 4 TB offset, physical and virtual address space limits are 30 * extended to 43-bits. 31 */ 32 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43) 33 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43) 34 35 #if CSS_USE_SCMI_SDS_DRIVER 36 #define MORELLO_SCMI_PAYLOAD_BASE ULL(0x45400000) 37 #else 38 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE ULL(0x45400000) 39 #endif 40 41 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00080000) 42 #define PLAT_ARM_MAX_BL31_SIZE UL(0x20000) 43 44 /******************************************************************************* 45 * MORELLO topology related constants 46 ******************************************************************************/ 47 #define MORELLO_MAX_CPUS_PER_CLUSTER U(2) 48 #define PLAT_ARM_CLUSTER_COUNT U(2) 49 #define PLAT_MORELLO_CHIP_COUNT U(1) 50 #define MORELLO_MAX_CLUSTERS_PER_CHIP U(2) 51 #define MORELLO_MAX_PE_PER_CPU U(1) 52 53 #define PLATFORM_CORE_COUNT (PLAT_MORELLO_CHIP_COUNT * \ 54 PLAT_ARM_CLUSTER_COUNT * \ 55 MORELLO_MAX_CPUS_PER_CLUSTER * \ 56 MORELLO_MAX_PE_PER_CPU) 57 58 /* System power domain level */ 59 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 60 61 /* 62 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 63 * plat_arm_mmap array defined for each BL stage. 64 */ 65 #define PLAT_ARM_MMAP_ENTRIES U(9) 66 #define MAX_XLAT_TABLES U(10) 67 68 #define PLATFORM_STACK_SIZE U(0x400) 69 70 #define PLAT_ARM_NSTIMER_FRAME_ID U(0) 71 #define PLAT_CSS_MHU_BASE UL(0x45000000) 72 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 73 #define PLAT_MAX_PWR_LVL U(2) 74 75 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 76 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 77 78 #define MORELLO_DEVICE_BASE ULL(0x08000000) 79 #define MORELLO_DEVICE_SIZE ULL(0x48000000) 80 81 #define MORELLO_MAP_DEVICE MAP_REGION_FLAT( \ 82 MORELLO_DEVICE_BASE, \ 83 MORELLO_DEVICE_SIZE, \ 84 MT_DEVICE | MT_RW | MT_SECURE) 85 86 #define ARM_MAP_DRAM1 MAP_REGION_FLAT( \ 87 ARM_DRAM1_BASE, \ 88 ARM_DRAM1_SIZE, \ 89 MT_MEMORY | MT_RW | MT_NS) 90 91 /* GIC related constants */ 92 #define PLAT_ARM_GICD_BASE UL(0x30000000) 93 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 94 #define PLAT_ARM_GICR_BASE UL(0x300C0000) 95 96 /* Number of SCMI channels on the platform */ 97 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 98 99 #endif /* PLATFORM_DEF_H */ 100