1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 12 #include <sgi_soc_platform_def.h> 13 14 #define PLAT_ARM_CLUSTER_COUNT U(16) 15 #define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1) 16 #define CSS_SGI_MAX_PE_PER_CPU U(1) 17 18 #define PLAT_CSS_MHU_BASE UL(0x45400000) 19 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 20 21 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 22 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 23 24 /* TZC Related Constants */ 25 #define PLAT_ARM_TZC_BASE UL(0x21830000) 26 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 27 28 #define TZC400_OFFSET UL(0x1000000) 29 #define TZC400_COUNT 4 30 31 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 32 (n * TZC400_OFFSET)) 33 34 #define TZC_NSAID_ALL_AP U(0) 35 #define TZC_NSAID_PCI U(1) 36 #define TZC_NSAID_HDLCD0 U(2) 37 #define TZC_NSAID_CLCD U(7) 38 #define TZC_NSAID_AP U(9) 39 #define TZC_NSAID_VIRTIO U(15) 40 41 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 42 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \ 43 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \ 44 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \ 45 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \ 46 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \ 47 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO)) 48 49 /* 50 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 51 */ 52 #ifdef __aarch64__ 53 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 42) 54 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 42) 55 #else 56 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 57 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 58 #endif 59 60 /* GIC related constants */ 61 #define PLAT_ARM_GICD_BASE UL(0x30000000) 62 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 63 #define PLAT_ARM_GICR_BASE UL(0x30140000) 64 65 #endif /* PLATFORM_DEF_H */ 66