1/*
2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6/dts-v1/;
7
8/ {
9	compatible = "arm,ffa-core-manifest-1.0";
10	#address-cells = <2>;
11	#size-cells = <1>;
12
13	attribute {
14		spmc_id = <0x8000>;
15		maj_ver = <0x1>;
16		min_ver = <0x1>;
17		exec_state = <0x0>;
18		load_address = <0x0 0xfd000000>;
19		entrypoint = <0x0 0xfd000000>;
20		binary_size = <0x80000>;
21	};
22
23	hypervisor {
24		compatible = "hafnium,hafnium";
25		vm1 {
26			is_ffa_partition;
27			debug_name = "op-tee";
28			load_address = <0xfd280000>;
29			vcpu_count = <8>;
30#ifdef TS_SP_FW_CONFIG
31			mem_size = <26738688>; /* 25MB TZC DRAM */
32#else
33			mem_size = <30928896>; /* 29MB TZC DRAM */
34#endif
35		};
36#ifdef TS_SP_FW_CONFIG
37		vm2 {
38			is_ffa_partition;
39			debug_name = "internal-trusted-storage";
40			load_address = <0xfee00000>;
41			vcpu_count = <1>;
42			mem_size = <2097152>; /* 2MB TZC DRAM */
43		};
44		vm3 {
45			is_ffa_partition;
46			debug_name = "crypto";
47			load_address = <0xfec00000>;
48			vcpu_count = <1>;
49			mem_size = <2097152>; /* 2MB TZC DRAM */
50		};
51#endif
52	};
53
54	cpus {
55		#address-cells = <0x2>;
56		#size-cells = <0x0>;
57
58		CPU0:cpu@0 {
59			device_type = "cpu";
60			compatible = "arm,armv8";
61			reg = <0x0 0x0>;
62			enable-method = "psci";
63		};
64
65		/*
66		 * SPMC (Hafnium) requires secondary cpu nodes are declared in
67		 * descending order
68		 */
69		CPU7:cpu@700 {
70			device_type = "cpu";
71			compatible = "arm,armv8";
72			reg = <0x0 0x700>;
73			enable-method = "psci";
74		};
75
76		CPU6:cpu@600 {
77			device_type = "cpu";
78			compatible = "arm,armv8";
79			reg = <0x0 0x600>;
80			enable-method = "psci";
81		};
82
83		CPU5:cpu@500 {
84			device_type = "cpu";
85			compatible = "arm,armv8";
86			reg = <0x0 0x500>;
87			enable-method = "psci";
88		};
89
90		CPU4:cpu@400 {
91			device_type = "cpu";
92			compatible = "arm,armv8";
93			reg = <0x0 0x400>;
94			enable-method = "psci";
95		};
96
97		CPU3:cpu@300 {
98			device_type = "cpu";
99			compatible = "arm,armv8";
100			reg = <0x0 0x300>;
101			enable-method = "psci";
102		};
103
104		CPU2:cpu@200 {
105			device_type = "cpu";
106			compatible = "arm,armv8";
107			reg = <0x0 0x200>;
108			enable-method = "psci";
109		};
110
111		CPU1:cpu@100 {
112			device_type = "cpu";
113			compatible = "arm,armv8";
114			reg = <0x0 0x100>;
115			enable-method = "psci";
116		};
117	};
118
119	/* 32MB of TC_TZC_DRAM1_BASE */
120	memory@fd000000 {
121		device_type = "memory";
122		reg = <0x0 0xfd000000 0x2000000>;
123	};
124};
125