1 /*
2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <drivers/generic_delay_timer.h>
10 #include <plat/arm/common/plat_arm.h>
11 #include <plat/common/platform.h>
12 #include <platform_def.h>
13
14 #pragma weak bl2_el3_early_platform_setup
15 #pragma weak bl2_el3_plat_arch_setup
16 #pragma weak bl2_el3_plat_prepare_exit
17
18 #define MAP_BL2_EL3_TOTAL MAP_REGION_FLAT( \
19 bl2_el3_tzram_layout.total_base, \
20 bl2_el3_tzram_layout.total_size, \
21 MT_MEMORY | MT_RW | MT_SECURE)
22
23 static meminfo_t bl2_el3_tzram_layout;
24
25 /*
26 * Perform arm specific early platform setup. At this moment we only initialize
27 * the console and the memory layout.
28 */
arm_bl2_el3_early_platform_setup(void)29 void arm_bl2_el3_early_platform_setup(void)
30 {
31 /* Initialize the console to provide early debug support */
32 arm_console_boot_init();
33
34 /*
35 * Allow BL2 to see the whole Trusted RAM. This is determined
36 * statically since we cannot rely on BL1 passing this information
37 * in the BL2_AT_EL3 case.
38 */
39 bl2_el3_tzram_layout.total_base = ARM_BL_RAM_BASE;
40 bl2_el3_tzram_layout.total_size = ARM_BL_RAM_SIZE;
41
42 /* Initialise the IO layer and register platform IO devices */
43 plat_arm_io_setup();
44 }
45
bl2_el3_early_platform_setup(u_register_t arg0 __unused,u_register_t arg1 __unused,u_register_t arg2 __unused,u_register_t arg3 __unused)46 void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
47 u_register_t arg1 __unused,
48 u_register_t arg2 __unused,
49 u_register_t arg3 __unused)
50 {
51 arm_bl2_el3_early_platform_setup();
52
53 /*
54 * Initialize Interconnect for this cluster during cold boot.
55 * No need for locks as no other CPU is active.
56 */
57 plat_arm_interconnect_init();
58 /*
59 * Enable Interconnect coherency for the primary CPU's cluster.
60 */
61 plat_arm_interconnect_enter_coherency();
62
63 generic_delay_timer_init();
64 }
65
66 /*******************************************************************************
67 * Perform the very early platform specific architectural setup here. At the
68 * moment this is only initializes the mmu in a quick and dirty way.
69 ******************************************************************************/
arm_bl2_el3_plat_arch_setup(void)70 void arm_bl2_el3_plat_arch_setup(void)
71 {
72
73 #if USE_COHERENT_MEM
74 /* Ensure ARM platforms dont use coherent memory in BL2_AT_EL3 */
75 assert(BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE == 0U);
76 #endif
77
78 const mmap_region_t bl_regions[] = {
79 MAP_BL2_EL3_TOTAL,
80 ARM_MAP_BL_RO,
81 {0}
82 };
83
84 setup_page_tables(bl_regions, plat_arm_get_mmap());
85
86 #ifdef __aarch64__
87 enable_mmu_el3(0);
88 #else
89 enable_mmu_svc_mon(0);
90 #endif
91 }
92
bl2_el3_plat_arch_setup(void)93 void bl2_el3_plat_arch_setup(void)
94 {
95 arm_bl2_el3_plat_arch_setup();
96 }
97
bl2_el3_plat_prepare_exit(void)98 void bl2_el3_plat_prepare_exit(void)
99 {
100 }
101