1 /*
2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <libfdt.h>
10
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <drivers/arm/css/css_mhu_doorbell.h>
14 #include <drivers/arm/css/scmi.h>
15 #include <plat/arm/common/plat_arm.h>
16 #include <plat/common/platform.h>
17
18 #include <sgi_ras.h>
19 #include <sgi_variant.h>
20
21 sgi_platform_info_t sgi_plat_info;
22
23 static scmi_channel_plat_info_t sgi575_scmi_plat_info = {
24 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
25 .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
26 .db_preserve_mask = 0xfffffffe,
27 .db_modify_mask = 0x1,
28 .ring_doorbell = &mhu_ring_doorbell,
29 };
30
31 static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
32 {
33 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
34 .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
35 .db_preserve_mask = 0xfffffffe,
36 .db_modify_mask = 0x1,
37 .ring_doorbell = &mhuv2_ring_doorbell,
38 },
39 #if (CSS_SGI_CHIP_COUNT > 1)
40 {
41 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
42 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),
43 .db_reg_addr = PLAT_CSS_MHU_BASE
44 + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1) + SENDER_REG_SET(0),
45 .db_preserve_mask = 0xfffffffe,
46 .db_modify_mask = 0x1,
47 .ring_doorbell = &mhuv2_ring_doorbell,
48 },
49 #endif
50 #if (CSS_SGI_CHIP_COUNT > 2)
51 {
52 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
53 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),
54 .db_reg_addr = PLAT_CSS_MHU_BASE +
55 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2) + SENDER_REG_SET(0),
56 .db_preserve_mask = 0xfffffffe,
57 .db_modify_mask = 0x1,
58 .ring_doorbell = &mhuv2_ring_doorbell,
59 },
60 #endif
61 #if (CSS_SGI_CHIP_COUNT > 3)
62 {
63 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
64 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
65 .db_reg_addr = PLAT_CSS_MHU_BASE +
66 CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3) + SENDER_REG_SET(0),
67 .db_preserve_mask = 0xfffffffe,
68 .db_modify_mask = 0x1,
69 .ring_doorbell = &mhuv2_ring_doorbell,
70 },
71 #endif
72 };
73
plat_css_get_scmi_info(int channel_id)74 scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
75 {
76 if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
77 sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
78 sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
79 sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM) {
80 if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info))
81 panic();
82 return &plat_rd_scmi_info[channel_id];
83 }
84 else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM)
85 return &sgi575_scmi_plat_info;
86 else
87 panic();
88 }
89
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)90 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
91 u_register_t arg2, u_register_t arg3)
92 {
93 sgi_plat_info.platform_id = plat_arm_sgi_get_platform_id();
94 sgi_plat_info.config_id = plat_arm_sgi_get_config_id();
95 sgi_plat_info.multi_chip_mode = plat_arm_sgi_get_multi_chip_mode();
96
97 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
98 }
99
sgi_bl31_common_platform_setup(void)100 void sgi_bl31_common_platform_setup(void)
101 {
102 arm_bl31_platform_setup();
103
104 #if RAS_EXTENSION
105 sgi_ras_intr_handler_setup();
106 #endif
107 }
108
plat_arm_psci_override_pm_ops(plat_psci_ops_t * ops)109 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
110 {
111 /*
112 * For RD-E1-Edge, only CPU power ON/OFF, PSCI platform callbacks are
113 * supported.
114 */
115 if (((sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
116 (sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID))) {
117 ops->cpu_standby = NULL;
118 ops->system_off = NULL;
119 ops->system_reset = NULL;
120 ops->get_sys_suspend_power_state = NULL;
121 ops->pwr_domain_suspend = NULL;
122 ops->pwr_domain_suspend_finish = NULL;
123 }
124
125 return css_scmi_override_pm_ops(ops);
126 }
127