1 /*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <platform_def.h>
8
9 #include <common/bl_common.h>
10 #include <common/debug.h>
11 #include <plat/arm/common/plat_arm.h>
12
13 #include <sgm_variant.h>
14
15 /*
16 * Table of regions for different BL stages to map using the MMU.
17 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
18 * arm_configure_mmu_elx() will give the available subset of that.
19 */
20 #if IMAGE_BL1
21 const mmap_region_t plat_arm_mmap[] = {
22 ARM_MAP_SHARED_RAM,
23 V2M_MAP_FLASH0_RO,
24 V2M_MAP_IOFPGA,
25 CSS_MAP_DEVICE,
26 CSS_MAP_GIC_DEVICE,
27 SOC_CSS_MAP_DEVICE,
28 #if TRUSTED_BOARD_BOOT
29 ARM_MAP_NS_DRAM1,
30 #endif
31 {0}
32 };
33 #endif
34 #if IMAGE_BL2
35 const mmap_region_t plat_arm_mmap[] = {
36 ARM_MAP_SHARED_RAM,
37 V2M_MAP_FLASH0_RO,
38 V2M_MAP_IOFPGA,
39 CSS_MAP_DEVICE,
40 CSS_MAP_GIC_DEVICE,
41 SOC_CSS_MAP_DEVICE,
42 ARM_MAP_NS_DRAM1,
43 #ifdef SPD_tspd
44 ARM_MAP_TSP_SEC_MEM,
45 #endif
46 #ifdef SPD_opteed
47 ARM_OPTEE_PAGEABLE_LOAD_MEM,
48 #endif
49 #if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
50 ARM_MAP_BL1_RW,
51 #endif
52 {0}
53 };
54 #endif
55 #if IMAGE_BL2U
56 const mmap_region_t plat_arm_mmap[] = {
57 ARM_MAP_SHARED_RAM,
58 CSS_MAP_DEVICE,
59 CSS_MAP_GIC_DEVICE,
60 SOC_CSS_MAP_DEVICE,
61 {0}
62 };
63 #endif
64 #if IMAGE_BL31
65 const mmap_region_t plat_arm_mmap[] = {
66 ARM_MAP_SHARED_RAM,
67 V2M_MAP_IOFPGA,
68 CSS_MAP_DEVICE,
69 CSS_MAP_GIC_DEVICE,
70 SOC_CSS_MAP_DEVICE,
71 {0}
72 };
73 #endif
74 #if IMAGE_BL32
75 const mmap_region_t plat_arm_mmap[] = {
76 V2M_MAP_IOFPGA,
77 CSS_MAP_DEVICE,
78 CSS_MAP_GIC_DEVICE,
79 SOC_CSS_MAP_DEVICE,
80 {0}
81 };
82 #endif
83
84 ARM_CASSERT_MMAP
85
plat_arm_get_mmap(void)86 const mmap_region_t *plat_arm_get_mmap(void)
87 {
88 return plat_arm_mmap;
89 }
90