1 /* 2 * Copyright (c) 2016 - 2020, Broadcom 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdint.h> 8 9 #include <lib/mmio.h> 10 11 #include <platform_def.h> 12 13 #define ICFG_IPROC_IOPAD_CTRL_4 (IPROC_ROOT + 0x9c0) 14 #define ICFG_IPROC_IOPAD_CTRL_5 (IPROC_ROOT + 0x9c4) 15 #define ICFG_IPROC_IOPAD_CTRL_6 (IPROC_ROOT + 0x9c8) 16 #define ICFG_IPROC_IOPAD_CTRL_7 (IPROC_ROOT + 0x9cc) 17 18 #define IOPAD_CTRL4_SDIO0_CD_IND_R 30 19 #define IOPAD_CTRL4_SDIO0_CD_SRC_R 31 20 #define IOPAD_CTRL4_SDIO0_CD_HYS_R 29 21 #define IOPAD_CTRL4_SDIO0_CD_PULL_R 28 22 #define IOPAD_CTRL4_SDIO0_CD_DRIVE_R 24 23 #define IOPAD_CTRL4_SDIO0_CLK_SDCARD_SRC_R 23 24 #define IOPAD_CTRL4_SDIO0_CLK_SDCARD_HYS_R 21 25 #define IOPAD_CTRL4_SDIO0_CLK_SDCARD_DRIVE_R 17 26 27 #define IOPAD_CTRL4_SDIO0_DATA0_SRC_R 15 28 #define IOPAD_CTRL4_SDIO0_DATA0_HYS_R 13 29 #define IOPAD_CTRL4_SDIO0_DATA0_DRIVE_R 9 30 #define IOPAD_CTRL4_SDIO0_DATA1_SRC_R 7 31 #define IOPAD_CTRL4_SDIO0_DATA1_HYS_R 5 32 #define IOPAD_CTRL4_SDIO0_DATA1_DRIVE_R 1 33 34 #define IOPAD_CTRL5_SDIO0_DATA2_SRC_R 31 35 #define IOPAD_CTRL5_SDIO0_DATA2_HYS_R 29 36 #define IOPAD_CTRL5_SDIO0_DATA2_DRIVE_R 25 37 #define IOPAD_CTRL5_SDIO0_DATA3_SRC_R 23 38 #define IOPAD_CTRL5_SDIO0_DATA3_IND_R 22 39 #define IOPAD_CTRL5_SDIO0_DATA3_HYS_R 21 40 #define IOPAD_CTRL5_SDIO0_DATA3_DRIVE_R 17 41 #define IOPAD_CTRL5_SDIO0_DATA4_SRC_R 15 42 #define IOPAD_CTRL5_SDIO0_DATA4_HYS_R 13 43 #define IOPAD_CTRL5_SDIO0_DATA4_DRIVE_R 9 44 #define IOPAD_CTRL5_SDIO0_DATA5_SRC_R 7 45 #define IOPAD_CTRL5_SDIO0_DATA5_HYS_R 5 46 #define IOPAD_CTRL5_SDIO0_DATA5_DRIVE_R 1 47 48 #define IOPAD_CTRL6_SDIO0_DATA6_SRC_R 31 49 #define IOPAD_CTRL6_SDIO0_DATA6_HYS_R 29 50 #define IOPAD_CTRL6_SDIO0_DATA6_DRIVE_R 25 51 #define IOPAD_CTRL6_SDIO0_DATA7_SRC_R 23 52 #define IOPAD_CTRL6_SDIO0_DATA7_HYS_R 21 53 #define IOPAD_CTRL6_SDIO0_DATA7_DRIVE_R 17 54 emmc_soft_reset(void)55void emmc_soft_reset(void) 56 { 57 uint32_t val = 0; 58 59 val = (BIT(IOPAD_CTRL6_SDIO0_DATA7_SRC_R) | 60 BIT(IOPAD_CTRL6_SDIO0_DATA7_HYS_R) | 61 BIT(IOPAD_CTRL6_SDIO0_DATA7_DRIVE_R) | 62 BIT(IOPAD_CTRL6_SDIO0_DATA6_SRC_R) | 63 BIT(IOPAD_CTRL6_SDIO0_DATA6_HYS_R) | 64 BIT(IOPAD_CTRL6_SDIO0_DATA6_DRIVE_R)); 65 66 mmio_write_32(ICFG_IPROC_IOPAD_CTRL_6, val); 67 68 val = (BIT(IOPAD_CTRL5_SDIO0_DATA3_SRC_R) | 69 BIT(IOPAD_CTRL5_SDIO0_DATA3_HYS_R) | 70 BIT(IOPAD_CTRL5_SDIO0_DATA3_DRIVE_R) | 71 BIT(IOPAD_CTRL5_SDIO0_DATA4_SRC_R) | 72 BIT(IOPAD_CTRL5_SDIO0_DATA4_HYS_R) | 73 BIT(IOPAD_CTRL5_SDIO0_DATA4_DRIVE_R) | 74 BIT(IOPAD_CTRL5_SDIO0_DATA5_SRC_R) | 75 BIT(IOPAD_CTRL5_SDIO0_DATA5_HYS_R) | 76 BIT(IOPAD_CTRL5_SDIO0_DATA5_DRIVE_R)); 77 78 mmio_write_32(ICFG_IPROC_IOPAD_CTRL_5, val); 79 80 val = (BIT(IOPAD_CTRL4_SDIO0_DATA0_SRC_R) | 81 BIT(IOPAD_CTRL4_SDIO0_DATA0_HYS_R) | 82 BIT(IOPAD_CTRL4_SDIO0_DATA0_DRIVE_R) | 83 BIT(IOPAD_CTRL4_SDIO0_DATA1_SRC_R) | 84 BIT(IOPAD_CTRL4_SDIO0_DATA1_HYS_R) | 85 BIT(IOPAD_CTRL4_SDIO0_DATA1_DRIVE_R) | 86 BIT(IOPAD_CTRL5_SDIO0_DATA2_SRC_R) | 87 BIT(IOPAD_CTRL5_SDIO0_DATA2_HYS_R) | 88 BIT(IOPAD_CTRL5_SDIO0_DATA2_DRIVE_R)); 89 90 mmio_write_32(ICFG_IPROC_IOPAD_CTRL_6, val); 91 92 val = (BIT(IOPAD_CTRL4_SDIO0_CLK_SDCARD_SRC_R) | 93 BIT(IOPAD_CTRL4_SDIO0_CLK_SDCARD_HYS_R) | 94 BIT(IOPAD_CTRL4_SDIO0_CLK_SDCARD_DRIVE_R) | 95 BIT(IOPAD_CTRL4_SDIO0_CD_SRC_R) | 96 BIT(IOPAD_CTRL4_SDIO0_CD_HYS_R)); 97 98 /* 99 * set pull-down, clear pull-up=0 100 * bit 12: pull-down bit 11: pull-up 101 * Note: In emulation, this pull-down setting was not 102 * sufficient. Board design likely requires pull down on 103 * this pin for eMMC. 104 */ 105 106 val |= BIT(IOPAD_CTRL4_SDIO0_CD_PULL_R); 107 108 mmio_write_32(ICFG_IPROC_IOPAD_CTRL_4, val); 109 } 110