1 /*
2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <string.h>
10
11 #include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/
12
13 #include <arch_helpers.h>
14 #include <common/bl_common.h>
15 #include <common/debug.h>
16 #include <common/desc_image_load.h>
17 #include <drivers/arm/pl011.h>
18 #include <drivers/delay_timer.h>
19 #include <drivers/mmc.h>
20 #include <drivers/synopsys/dw_mmc.h>
21 #include <lib/mmio.h>
22 #ifdef SPD_opteed
23 #include <lib/optee_utils.h>
24 #endif
25 #include <plat/common/platform.h>
26
27 #include <hi6220.h>
28 #include <hisi_mcu.h>
29 #include <hisi_sram_map.h>
30 #include "hikey_private.h"
31
32 #define BL2_RW_BASE (BL_CODE_END)
33
34 static meminfo_t bl2_el3_tzram_layout;
35 static console_t console;
36 static struct mmc_device_info mmc_info;
37
38 enum {
39 BOOT_MODE_RECOVERY = 0,
40 BOOT_MODE_NORMAL,
41 BOOT_MODE_MASK = 1,
42 };
43
44 /*******************************************************************************
45 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
46 * Return 0 on success, -1 otherwise.
47 ******************************************************************************/
plat_hikey_bl2_handle_scp_bl2(image_info_t * scp_bl2_image_info)48 int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
49 {
50 /* Enable MCU SRAM */
51 hisi_mcu_enable_sram();
52
53 /* Load MCU binary into SRAM */
54 hisi_mcu_load_image(scp_bl2_image_info->image_base,
55 scp_bl2_image_info->image_size);
56 /* Let MCU running */
57 hisi_mcu_start_run();
58
59 INFO("%s: MCU PC is at 0x%x\n",
60 __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2));
61 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is 0x%x\n",
62 __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4));
63 return 0;
64 }
65
66 /*******************************************************************************
67 * Gets SPSR for BL32 entry
68 ******************************************************************************/
hikey_get_spsr_for_bl32_entry(void)69 uint32_t hikey_get_spsr_for_bl32_entry(void)
70 {
71 /*
72 * The Secure Payload Dispatcher service is responsible for
73 * setting the SPSR prior to entry into the BL3-2 image.
74 */
75 return 0;
76 }
77
78 /*******************************************************************************
79 * Gets SPSR for BL33 entry
80 ******************************************************************************/
81 #ifdef __aarch64__
hikey_get_spsr_for_bl33_entry(void)82 uint32_t hikey_get_spsr_for_bl33_entry(void)
83 {
84 unsigned int mode;
85 uint32_t spsr;
86
87 /* Figure out what mode we enter the non-secure world in */
88 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
89
90 /*
91 * TODO: Consider the possibility of specifying the SPSR in
92 * the FIP ToC and allowing the platform to have a say as
93 * well.
94 */
95 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
96 return spsr;
97 }
98 #else
hikey_get_spsr_for_bl33_entry(void)99 uint32_t hikey_get_spsr_for_bl33_entry(void)
100 {
101 unsigned int hyp_status, mode, spsr;
102
103 hyp_status = GET_VIRT_EXT(read_id_pfr1());
104
105 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
106
107 /*
108 * TODO: Consider the possibility of specifying the SPSR in
109 * the FIP ToC and allowing the platform to have a say as
110 * well.
111 */
112 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
113 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
114 return spsr;
115 }
116 #endif /* __aarch64__ */
117
bl2_plat_handle_pre_image_load(unsigned int image_id)118 int bl2_plat_handle_pre_image_load(unsigned int image_id)
119 {
120 return hikey_set_fip_addr(image_id, "fastboot");
121 }
122
hikey_bl2_handle_post_image_load(unsigned int image_id)123 int hikey_bl2_handle_post_image_load(unsigned int image_id)
124 {
125 int err = 0;
126 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
127 #ifdef SPD_opteed
128 bl_mem_params_node_t *pager_mem_params = NULL;
129 bl_mem_params_node_t *paged_mem_params = NULL;
130 #endif
131 assert(bl_mem_params);
132
133 switch (image_id) {
134 #ifdef __aarch64__
135 case BL32_IMAGE_ID:
136 #ifdef SPD_opteed
137 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
138 assert(pager_mem_params);
139
140 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
141 assert(paged_mem_params);
142
143 err = parse_optee_header(&bl_mem_params->ep_info,
144 &pager_mem_params->image_info,
145 &paged_mem_params->image_info);
146 if (err != 0) {
147 WARN("OPTEE header parse error.\n");
148 }
149 #endif
150 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl32_entry();
151 break;
152 #endif
153
154 case BL33_IMAGE_ID:
155 /* BL33 expects to receive the primary CPU MPID (through r0) */
156 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
157 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl33_entry();
158 break;
159
160 #ifdef SCP_BL2_BASE
161 case SCP_BL2_IMAGE_ID:
162 /* The subsequent handling of SCP_BL2 is platform specific */
163 err = plat_hikey_bl2_handle_scp_bl2(&bl_mem_params->image_info);
164 if (err) {
165 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
166 }
167 break;
168 #endif
169 default:
170 /* Do nothing in default case */
171 break;
172 }
173
174 return err;
175 }
176
177 /*******************************************************************************
178 * This function can be used by the platforms to update/use image
179 * information for given `image_id`.
180 ******************************************************************************/
bl2_plat_handle_post_image_load(unsigned int image_id)181 int bl2_plat_handle_post_image_load(unsigned int image_id)
182 {
183 return hikey_bl2_handle_post_image_load(image_id);
184 }
185
reset_dwmmc_clk(void)186 static void reset_dwmmc_clk(void)
187 {
188 unsigned int data;
189
190 /* disable mmc0 bus clock */
191 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0);
192 do {
193 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
194 } while (data & PERI_CLK0_MMC0);
195 /* enable mmc0 bus clock */
196 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0);
197 do {
198 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
199 } while (!(data & PERI_CLK0_MMC0));
200 /* reset mmc0 clock domain */
201 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0);
202
203 /* bypass mmc0 clock phase */
204 data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
205 data |= 3;
206 mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
207
208 /* disable low power */
209 data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
210 data |= 1 << 3;
211 mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
212 do {
213 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
214 } while (!(data & PERI_RST0_MMC0));
215
216 /* unreset mmc0 clock domain */
217 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0);
218 do {
219 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
220 } while (data & PERI_RST0_MMC0);
221 }
222
hikey_boardid_init(void)223 static void hikey_boardid_init(void)
224 {
225 u_register_t midr;
226
227 midr = read_midr();
228 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr);
229 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR,
230 (unsigned int)midr);
231
232 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0);
233 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b);
234
235 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234);
236 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678);
237 }
238
hikey_sd_init(void)239 static void hikey_sd_init(void)
240 {
241 /* switch pinmux to SD */
242 mmio_write_32(IOMG_SD_CLK, IOMG_MUX_FUNC0);
243 mmio_write_32(IOMG_SD_CMD, IOMG_MUX_FUNC0);
244 mmio_write_32(IOMG_SD_DATA0, IOMG_MUX_FUNC0);
245 mmio_write_32(IOMG_SD_DATA1, IOMG_MUX_FUNC0);
246 mmio_write_32(IOMG_SD_DATA2, IOMG_MUX_FUNC0);
247 mmio_write_32(IOMG_SD_DATA3, IOMG_MUX_FUNC0);
248
249 mmio_write_32(IOCG_SD_CLK, IOCG_INPUT_16MA);
250 mmio_write_32(IOCG_SD_CMD, IOCG_INPUT_12MA);
251 mmio_write_32(IOCG_SD_DATA0, IOCG_INPUT_12MA);
252 mmio_write_32(IOCG_SD_DATA1, IOCG_INPUT_12MA);
253 mmio_write_32(IOCG_SD_DATA2, IOCG_INPUT_12MA);
254 mmio_write_32(IOCG_SD_DATA3, IOCG_INPUT_12MA);
255
256 /* set SD Card detect as nopull */
257 mmio_write_32(IOCG_GPIO8, 0);
258 }
259
hikey_jumper_init(void)260 static void hikey_jumper_init(void)
261 {
262 /* set jumper detect as nopull */
263 mmio_write_32(IOCG_GPIO24, 0);
264 /* set jumper detect as GPIO */
265 mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0);
266 }
267
bl2_el3_early_platform_setup(u_register_t arg1,u_register_t arg2,u_register_t arg3,u_register_t arg4)268 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
269 u_register_t arg3, u_register_t arg4)
270 {
271 /* Initialize the console to provide early debug support */
272 console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ,
273 PL011_BAUDRATE, &console);
274 /*
275 * Allow BL2 to see the whole Trusted RAM.
276 */
277 bl2_el3_tzram_layout.total_base = BL2_RW_BASE;
278 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE;
279 }
280
bl2_el3_plat_arch_setup(void)281 void bl2_el3_plat_arch_setup(void)
282 {
283 hikey_init_mmu_el3(bl2_el3_tzram_layout.total_base,
284 bl2_el3_tzram_layout.total_size,
285 BL_CODE_BASE,
286 BL_CODE_END,
287 BL_COHERENT_RAM_BASE,
288 BL_COHERENT_RAM_END);
289 }
290
bl2_platform_setup(void)291 void bl2_platform_setup(void)
292 {
293 dw_mmc_params_t params;
294
295 hikey_sp804_init();
296 hikey_gpio_init();
297 hikey_pmussi_init();
298 hikey_hi6553_init();
299 /* Clear SRAM since it'll be used by MCU right now. */
300 memset((void *)SRAM_BASE, 0, SRAM_SIZE);
301
302 dsb();
303 hikey_ddr_init(DDR_FREQ_800M);
304 hikey_security_setup();
305
306 hikey_boardid_init();
307 init_acpu_dvfs();
308 hikey_rtc_init();
309 hikey_sd_init();
310 hikey_jumper_init();
311
312 hikey_mmc_pll_init();
313
314 /* Clean SRAM before MCU used */
315 clean_dcache_range(SRAM_BASE, SRAM_SIZE);
316
317 reset_dwmmc_clk();
318 memset(¶ms, 0, sizeof(dw_mmc_params_t));
319 params.reg_base = DWMMC0_BASE;
320 params.desc_base = HIKEY_MMC_DESC_BASE;
321 params.desc_size = 1 << 20;
322 params.clk_rate = 24 * 1000 * 1000;
323 params.bus_width = MMC_BUS_WIDTH_8;
324 params.flags = MMC_FLAG_CMD23;
325 mmc_info.mmc_dev_type = MMC_IS_EMMC;
326 dw_mmc_init(¶ms, &mmc_info);
327
328 hikey_io_setup();
329 }
330