1 /*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <drivers/arm/pl061_gpio.h>
9 #include <drivers/arm/sp804_delay_timer.h>
10 #include <drivers/gpio.h>
11 #include <lib/mmio.h>
12
13 #include <hi6220.h>
14 #include <hi6553.h>
15 #include "hikey_private.h"
16
hikey_sp804_init(void)17 void hikey_sp804_init(void)
18 {
19 uint32_t data;
20
21 /* select the clock of dual timer0 */
22 data = mmio_read_32(AO_SC_TIMER_EN0);
23 while (data & 3) {
24 data &= ~3;
25 data |= 3 << 16;
26 mmio_write_32(AO_SC_TIMER_EN0, data);
27 data = mmio_read_32(AO_SC_TIMER_EN0);
28 }
29 /* enable the pclk of dual timer0 */
30 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4);
31 while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)) {
32 mmio_write_32(AO_SC_PERIPH_CLKEN4, PCLK_TIMER1 | PCLK_TIMER0);
33 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4);
34 }
35 /* reset dual timer0 */
36 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
37 mmio_write_32(AO_SC_PERIPH_RSTEN4, PCLK_TIMER1 | PCLK_TIMER0);
38 do {
39 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
40 } while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0));
41 /* unreset dual timer0 */
42 mmio_write_32(AO_SC_PERIPH_RSTDIS4, PCLK_TIMER1 | PCLK_TIMER0);
43 do {
44 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
45 } while ((data & PCLK_TIMER1) || (data & PCLK_TIMER0));
46
47 sp804_timer_init(SP804_TIMER0_BASE, 10, 192);
48 }
49
hikey_gpio_init(void)50 void hikey_gpio_init(void)
51 {
52 pl061_gpio_init();
53 pl061_gpio_register(GPIO0_BASE, 0);
54 pl061_gpio_register(GPIO1_BASE, 1);
55 pl061_gpio_register(GPIO2_BASE, 2);
56 pl061_gpio_register(GPIO3_BASE, 3);
57 pl061_gpio_register(GPIO4_BASE, 4);
58 pl061_gpio_register(GPIO5_BASE, 5);
59 pl061_gpio_register(GPIO6_BASE, 6);
60 pl061_gpio_register(GPIO7_BASE, 7);
61 pl061_gpio_register(GPIO8_BASE, 8);
62 pl061_gpio_register(GPIO9_BASE, 9);
63 pl061_gpio_register(GPIO10_BASE, 10);
64 pl061_gpio_register(GPIO11_BASE, 11);
65 pl061_gpio_register(GPIO12_BASE, 12);
66 pl061_gpio_register(GPIO13_BASE, 13);
67 pl061_gpio_register(GPIO14_BASE, 14);
68 pl061_gpio_register(GPIO15_BASE, 15);
69 pl061_gpio_register(GPIO16_BASE, 16);
70 pl061_gpio_register(GPIO17_BASE, 17);
71 pl061_gpio_register(GPIO18_BASE, 18);
72 pl061_gpio_register(GPIO19_BASE, 19);
73
74 /* Power on indicator LED (USER_LED1). */
75 gpio_set_direction(32, GPIO_DIR_OUT); /* LED1 */
76 gpio_set_value(32, GPIO_LEVEL_HIGH);
77 gpio_set_direction(33, GPIO_DIR_OUT); /* LED2 */
78 gpio_set_value(33, GPIO_LEVEL_LOW);
79 gpio_set_direction(34, GPIO_DIR_OUT); /* LED3 */
80 gpio_set_direction(35, GPIO_DIR_OUT); /* LED4 */
81 }
82
hikey_pmussi_init(void)83 void hikey_pmussi_init(void)
84 {
85 uint32_t data;
86
87 /* Initialize PWR_HOLD GPIO */
88 gpio_set_direction(0, GPIO_DIR_OUT);
89 gpio_set_value(0, GPIO_LEVEL_LOW);
90
91 /*
92 * After reset, PMUSSI stays in reset mode.
93 * Now make it out of reset.
94 */
95 mmio_write_32(AO_SC_PERIPH_RSTDIS4,
96 AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N);
97 do {
98 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
99 } while (data & AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N);
100
101 /* Set PMUSSI clock latency for read operation. */
102 data = mmio_read_32(AO_SC_MCU_SUBSYS_CTRL3);
103 data &= ~AO_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
104 data |= AO_SC_MCU_SUBSYS_CTRL3_RCLK_3;
105 mmio_write_32(AO_SC_MCU_SUBSYS_CTRL3, data);
106
107 /* enable PMUSSI clock */
108 data = AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU |
109 AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_MCU;
110 mmio_write_32(AO_SC_PERIPH_CLKEN5, data);
111 data = AO_SC_PERIPH_CLKEN4_PCLK_PMUSSI;
112 mmio_write_32(AO_SC_PERIPH_CLKEN4, data);
113
114 gpio_set_value(0, GPIO_LEVEL_HIGH);
115 }
116
hikey_hi6553_init(void)117 void hikey_hi6553_init(void)
118 {
119 uint8_t data;
120
121 mmio_write_8(HI6553_PERI_EN_MARK, 0x1e);
122 mmio_write_8(HI6553_NP_REG_ADJ1, 0);
123 data = DISABLE6_XO_CLK_CONN | DISABLE6_XO_CLK_NFC |
124 DISABLE6_XO_CLK_RF1 | DISABLE6_XO_CLK_RF2;
125 mmio_write_8(HI6553_DISABLE6_XO_CLK, data);
126
127 /* configure BUCK0 & BUCK1 */
128 mmio_write_8(HI6553_BUCK01_CTRL2, 0x5e);
129 mmio_write_8(HI6553_BUCK0_CTRL7, 0x10);
130 mmio_write_8(HI6553_BUCK1_CTRL7, 0x10);
131 mmio_write_8(HI6553_BUCK0_CTRL5, 0x1e);
132 mmio_write_8(HI6553_BUCK1_CTRL5, 0x1e);
133 mmio_write_8(HI6553_BUCK0_CTRL1, 0xfc);
134 mmio_write_8(HI6553_BUCK1_CTRL1, 0xfc);
135
136 /* configure BUCK2 */
137 mmio_write_8(HI6553_BUCK2_REG1, 0x4f);
138 mmio_write_8(HI6553_BUCK2_REG5, 0x99);
139 mmio_write_8(HI6553_BUCK2_REG6, 0x45);
140 mdelay(1);
141 mmio_write_8(HI6553_VSET_BUCK2_ADJ, 0x22);
142 mdelay(1);
143
144 /* configure BUCK3 */
145 mmio_write_8(HI6553_BUCK3_REG3, 0x02);
146 mmio_write_8(HI6553_BUCK3_REG5, 0x99);
147 mmio_write_8(HI6553_BUCK3_REG6, 0x41);
148 mmio_write_8(HI6553_VSET_BUCK3_ADJ, 0x02);
149 mdelay(1);
150
151 /* configure BUCK4 */
152 mmio_write_8(HI6553_BUCK4_REG2, 0x9a);
153 mmio_write_8(HI6553_BUCK4_REG5, 0x99);
154 mmio_write_8(HI6553_BUCK4_REG6, 0x45);
155
156 /* configure LDO20 */
157 mmio_write_8(HI6553_LDO20_REG_ADJ, 0x50);
158
159 mmio_write_8(HI6553_NP_REG_CHG, 0x0f);
160 mmio_write_8(HI6553_CLK_TOP0, 0x06);
161 mmio_write_8(HI6553_CLK_TOP3, 0xc0);
162 mmio_write_8(HI6553_CLK_TOP4, 0x00);
163
164 /* configure LDO7 & LDO10 for SD slot */
165 /* enable LDO7 */
166 data = mmio_read_8(HI6553_LDO7_REG_ADJ);
167 data = (data & 0xf8) | 0x2;
168 mmio_write_8(HI6553_LDO7_REG_ADJ, data);
169 mdelay(5);
170 mmio_write_8(HI6553_ENABLE2_LDO1_8, 1 << 6);
171 mdelay(5);
172 /* enable LDO10 */
173 data = mmio_read_8(HI6553_LDO10_REG_ADJ);
174 data = (data & 0xf8) | 0x5;
175 mmio_write_8(HI6553_LDO10_REG_ADJ, data);
176 mdelay(5);
177 mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 1);
178 mdelay(5);
179 /* enable LDO15 */
180 data = mmio_read_8(HI6553_LDO15_REG_ADJ);
181 data = (data & 0xf8) | 0x4;
182 mmio_write_8(HI6553_LDO15_REG_ADJ, data);
183 mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 6);
184 mdelay(5);
185 /* enable LDO19 */
186 data = mmio_read_8(HI6553_LDO19_REG_ADJ);
187 data |= 0x7;
188 mmio_write_8(HI6553_LDO19_REG_ADJ, data);
189 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 2);
190 mdelay(5);
191 /* enable LDO21 */
192 data = mmio_read_8(HI6553_LDO21_REG_ADJ);
193 data = (data & 0xf8) | 0x3;
194 mmio_write_8(HI6553_LDO21_REG_ADJ, data);
195 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 4);
196 mdelay(5);
197 /* enable LDO22 */
198 data = mmio_read_8(HI6553_LDO22_REG_ADJ);
199 data = (data & 0xf8) | 0x7;
200 mmio_write_8(HI6553_LDO22_REG_ADJ, data);
201 mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 5);
202 mdelay(5);
203
204 /* select 32.764KHz */
205 mmio_write_8(HI6553_CLK19M2_600_586_EN, 0x01);
206
207 /* Disable vbus_det interrupts */
208 data = mmio_read_8(HI6553_IRQ2_MASK);
209 data = data | 0x3;
210 mmio_write_8(HI6553_IRQ2_MASK, data);
211 }
212
init_mmc0_pll(void)213 void init_mmc0_pll(void)
214 {
215 unsigned int data;
216
217 /* select SYSPLL as the source of MMC0 */
218 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
219 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 5 | 1 << 21);
220 do {
221 data = mmio_read_32(PERI_SC_CLK_SEL0);
222 } while (!(data & (1 << 5)));
223 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
224 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 29);
225 do {
226 data = mmio_read_32(PERI_SC_CLK_SEL0);
227 } while (data & (1 << 13));
228
229 mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 0));
230 do {
231 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
232 } while (!(data & (1 << 0)));
233
234 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
235 data |= 1 << 1;
236 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
237
238 do {
239 mmio_write_32(PERI_SC_CLKCFG8BIT1, (1 << 7) | 0xb);
240 data = mmio_read_32(PERI_SC_CLKCFG8BIT1);
241 } while ((data & 0xb) != 0xb);
242 }
243
reset_mmc0_clk(void)244 void reset_mmc0_clk(void)
245 {
246 unsigned int data;
247
248 /* disable mmc0 bus clock */
249 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0);
250 do {
251 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
252 } while (data & PERI_CLK0_MMC0);
253 /* enable mmc0 bus clock */
254 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0);
255 do {
256 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
257 } while (!(data & PERI_CLK0_MMC0));
258 /* reset mmc0 clock domain */
259 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0);
260
261 /* bypass mmc0 clock phase */
262 data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
263 data |= 3;
264 mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
265
266 /* disable low power */
267 data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
268 data |= 1 << 3;
269 mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
270 do {
271 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
272 } while (!(data & PERI_RST0_MMC0));
273
274 /* unreset mmc0 clock domain */
275 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0);
276 do {
277 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
278 } while (data & PERI_RST0_MMC0);
279 }
280
init_media_clk(void)281 void init_media_clk(void)
282 {
283 unsigned int data, value;
284
285 data = mmio_read_32(PMCTRL_MEDPLLCTRL);
286 data |= 1;
287 mmio_write_32(PMCTRL_MEDPLLCTRL, data);
288
289 for (;;) {
290 data = mmio_read_32(PMCTRL_MEDPLLCTRL);
291 value = 1 << 28;
292 if ((data & value) == value)
293 break;
294 }
295
296 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
297 data = 1 << 10;
298 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
299 }
300
init_mmc1_pll(void)301 void init_mmc1_pll(void)
302 {
303 uint32_t data;
304
305 /* select SYSPLL as the source of MMC1 */
306 /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
307 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 11 | 1 << 27);
308 do {
309 data = mmio_read_32(PERI_SC_CLK_SEL0);
310 } while (!(data & (1 << 11)));
311 /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
312 mmio_write_32(PERI_SC_CLK_SEL0, 1 << 30);
313 do {
314 data = mmio_read_32(PERI_SC_CLK_SEL0);
315 } while (data & (1 << 14));
316
317 mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 1));
318 do {
319 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
320 } while (!(data & (1 << 1)));
321
322 data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
323 data |= 1 << 2;
324 mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
325
326 do {
327 /* 1.2GHz / 50 = 24MHz */
328 mmio_write_32(PERI_SC_CLKCFG8BIT2, 0x31 | (1 << 7));
329 data = mmio_read_32(PERI_SC_CLKCFG8BIT2);
330 } while ((data & 0x31) != 0x31);
331 }
332
reset_mmc1_clk(void)333 void reset_mmc1_clk(void)
334 {
335 unsigned int data;
336
337 /* disable mmc1 bus clock */
338 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC1);
339 do {
340 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
341 } while (data & PERI_CLK0_MMC1);
342 /* enable mmc1 bus clock */
343 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC1);
344 do {
345 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
346 } while (!(data & PERI_CLK0_MMC1));
347 /* reset mmc1 clock domain */
348 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC1);
349
350 /* bypass mmc1 clock phase */
351 data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
352 data |= 3 << 2;
353 mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
354
355 /* disable low power */
356 data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
357 data |= 1 << 4;
358 mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
359 do {
360 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
361 } while (!(data & PERI_RST0_MMC1));
362
363 /* unreset mmc0 clock domain */
364 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC1);
365 do {
366 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
367 } while (data & PERI_RST0_MMC1);
368 }
369
370 /* Initialize PLL of both eMMC and SD controllers. */
hikey_mmc_pll_init(void)371 void hikey_mmc_pll_init(void)
372 {
373 init_mmc0_pll();
374 reset_mmc0_clk();
375 init_media_clk();
376
377 dsb();
378
379 init_mmc1_pll();
380 reset_mmc1_clk();
381 }
382
hikey_rtc_init(void)383 void hikey_rtc_init(void)
384 {
385 uint32_t data;
386
387 data = mmio_read_32(AO_SC_PERIPH_CLKEN4);
388 data |= AO_SC_PERIPH_RSTDIS4_RESET_RTC0_N;
389 mmio_write_32(AO_SC_PERIPH_CLKEN4, data);
390 }
391