1/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <cortex_a53.h>
10#include <hi6220.h>
11#include <hisi_sram_map.h>
12
13	.global pm_asm_code
14	.global pm_asm_code_end
15	.global v7_asm
16	.global v7_asm_end
17
18func pm_asm_code _align=3
19	mov	x0, 0
20	msr	oslar_el1, x0
21
22	mrs	x0, CORTEX_A53_CPUACTLR_EL1
23	bic	x0, x0, #(CORTEX_A53_CPUACTLR_EL1_RADIS | \
24				CORTEX_A53_CPUACTLR_EL1_L1RADIS)
25	orr	x0, x0, #0x180000
26	orr	x0, x0, #0xe000
27	msr	CORTEX_A53_CPUACTLR_EL1, x0
28
29	mrs	x3, actlr_el3
30	orr	x3, x3, #ACTLR_EL3_L2ECTLR_BIT
31	msr	actlr_el3, x3
32
33	mrs	x3, actlr_el2
34	orr	x3, x3, #ACTLR_EL2_L2ECTLR_BIT
35	msr	actlr_el2, x3
36
37	ldr	x3, =PWRCTRL_ACPU_ASM_D_ARM_PARA_AD
38	mrs	x0, mpidr_el1
39	and	x1, x0, #MPIDR_CPU_MASK
40	and	x0, x0, #MPIDR_CLUSTER_MASK
41	add	x0, x1, x0, LSR #6
42pen:	ldr	x4, [x3, x0, LSL #3]
43	cbz	x4, pen
44
45	mov	x0, #0x0
46	mov	x1, #0x0
47	mov	x2, #0x0
48	mov	x3, #0x0
49	br	x4
50
51	.ltorg
52
53pm_asm_code_end:
54endfunc pm_asm_code
55
56	/*
57	 * By default, all cores in Hi6220 reset with aarch32 mode.
58	 * Now hardcode ARMv7 instructions to execute warm reset for
59	 * switching aarch64 mode.
60	 */
61	.align	3
62	.section .rodata.v7_asm, "aS"
63v7_asm:
64	.word	0xE1A00000	// nop
65	.word	0xE3A02003	// mov r2, #3
66	.word	0xEE0C2F50	// mcr 15, 0, r2, cr12, cr0, {2}
67	.word	0xE320F003	// wfi
68
69	.ltorg
70v7_asm_end:
71