1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 #include <hikey_def.h> 16 #include <hikey_layout.h> /* BL memory region sizes, etc */ 17 18 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 19 #define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 20 21 /* 22 * Generic platform constants 23 */ 24 25 /* Size of cacheable stacks */ 26 #define PLATFORM_STACK_SIZE 0x1000 27 28 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 29 30 #define PLATFORM_CACHE_LINE_SIZE 64 31 #define PLATFORM_CLUSTER_COUNT U(2) 32 #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) 33 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 34 PLATFORM_CORE_COUNT_PER_CLUSTER) 35 #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2) 36 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 37 PLATFORM_CLUSTER_COUNT + U(1)) 38 39 #define PLAT_MAX_RET_STATE U(1) 40 #define PLAT_MAX_OFF_STATE U(2) 41 42 #define MAX_IO_DEVICES 3 43 #define MAX_IO_HANDLES 4 44 /* eMMC RPMB and eMMC User Data */ 45 #define MAX_IO_BLOCK_DEVICES U(2) 46 47 /* GIC related constants (no GICR in GIC-400) */ 48 #define PLAT_ARM_GICD_BASE 0xF6801000 49 #define PLAT_ARM_GICC_BASE 0xF6802000 50 #define PLAT_ARM_GICH_BASE 0xF6804000 51 #define PLAT_ARM_GICV_BASE 0xF6806000 52 53 /* 54 * Platform specific page table and MMU setup constants 55 */ 56 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 57 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 58 59 #if defined(IMAGE_BL1) || defined(IMAGE_BL32) 60 #define MAX_XLAT_TABLES 3 61 #endif 62 63 #ifdef IMAGE_BL31 64 #define MAX_XLAT_TABLES 4 65 #endif 66 67 #ifdef IMAGE_BL2 68 #define MAX_XLAT_TABLES 4 69 #endif 70 71 #define MAX_MMAP_REGIONS 16 72 73 /* 74 * Declarations and constants to access the mailboxes safely. Each mailbox is 75 * aligned on the biggest cache line size in the platform. This is known only 76 * to the platform as it might have a combination of integrated and external 77 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 78 * line at any cache level. They could belong to different cpus/clusters & 79 * get written while being protected by different locks causing corruption of 80 * a valid mailbox address. 81 */ 82 #define CACHE_WRITEBACK_SHIFT 6 83 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 84 85 #endif /* PLATFORM_DEF_H */ 86