1 /*
2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9 #include <string.h>
10
11 #include <platform_def.h>
12
13 #include <arch_helpers.h>
14 #include <common/bl_common.h>
15 #include <common/debug.h>
16 #include <common/tbbr/tbbr_img_def.h>
17 #include <drivers/arm/pl011.h>
18 #include <drivers/arm/pl061_gpio.h>
19 #include <drivers/generic_delay_timer.h>
20 #include <drivers/mmc.h>
21 #include <drivers/synopsys/dw_mmc.h>
22 #include <lib/mmio.h>
23 #include <plat/common/platform.h>
24
25 #include "hi3798cv200.h"
26 #include "plat_private.h"
27
28 /* Data structure which holds the extents of the trusted RAM for BL1 */
29 static meminfo_t bl1_tzram_layout;
30 static meminfo_t bl2_tzram_layout;
31 static console_t console;
32
33 #if !POPLAR_RECOVERY
34 static struct mmc_device_info mmc_info;
35 #endif
36
37 /*
38 * Cannot use default weak implementation in bl1_main.c because BL1 RW data is
39 * not at the top of the secure memory.
40 */
bl1_plat_handle_post_image_load(unsigned int image_id)41 int bl1_plat_handle_post_image_load(unsigned int image_id)
42 {
43 image_desc_t *image_desc;
44 entry_point_info_t *ep_info;
45
46 if (image_id != BL2_IMAGE_ID)
47 return 0;
48
49 /* Get the image descriptor */
50 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
51 assert(image_desc != NULL);
52
53 /* Get the entry point info */
54 ep_info = &image_desc->ep_info;
55
56 bl2_tzram_layout.total_base = BL2_BASE;
57 bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE;
58
59 flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t));
60
61 ep_info->args.arg1 = (uintptr_t)&bl2_tzram_layout;
62
63 VERBOSE("BL1: BL2 memory layout address = %p\n",
64 (void *)&bl2_tzram_layout);
65
66 return 0;
67 }
68
bl1_early_platform_setup(void)69 void bl1_early_platform_setup(void)
70 {
71 /* Initialize the console to provide early debug support */
72 console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ,
73 PL011_BAUDRATE, &console);
74
75 /* Allow BL1 to see the whole Trusted RAM */
76 bl1_tzram_layout.total_base = BL1_RW_BASE;
77 bl1_tzram_layout.total_size = BL1_RW_SIZE;
78
79 INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
80 BL1_RAM_LIMIT - BL1_RAM_BASE);
81 }
82
bl1_plat_arch_setup(void)83 void bl1_plat_arch_setup(void)
84 {
85 plat_configure_mmu_el3(bl1_tzram_layout.total_base,
86 bl1_tzram_layout.total_size,
87 BL1_RO_BASE, /* l-loader and BL1 ROM */
88 BL1_RO_LIMIT,
89 BL_COHERENT_RAM_BASE,
90 BL_COHERENT_RAM_END);
91 }
92
bl1_platform_setup(void)93 void bl1_platform_setup(void)
94 {
95 int i;
96 #if !POPLAR_RECOVERY
97 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
98 #endif
99
100 generic_delay_timer_init();
101
102 pl061_gpio_init();
103 for (i = 0; i < GPIO_MAX; i++)
104 pl061_gpio_register(GPIO_BASE(i), i);
105
106 #if !POPLAR_RECOVERY
107 /* SoC-specific emmc register are initialized/configured by bootrom */
108 INFO("BL1: initializing emmc\n");
109 mmc_info.mmc_dev_type = MMC_IS_EMMC;
110 dw_mmc_init(¶ms, &mmc_info);
111 #endif
112
113 plat_io_setup();
114 }
115
bl1_plat_get_next_image_id(void)116 unsigned int bl1_plat_get_next_image_id(void)
117 {
118 return BL2_IMAGE_ID;
119 }
120