1 /*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdlib.h>
8 #include <stdint.h>
9 #include <stdbool.h>
10
11 #include <common/debug.h>
12 #include <drivers/delay_timer.h>
13 #include <lib/mmio.h>
14 #include <lib/psci/psci.h>
15 #include <lib/smccc.h>
16 #include <platform_def.h>
17 #include <services/std_svc.h>
18
19 #include <gpc.h>
20 #include <imx_sip_svc.h>
21
imx_gpc_init(void)22 void imx_gpc_init(void)
23 {
24 unsigned int val;
25 int i;
26
27 /* mask all the wakeup irq by default */
28 for (i = 0; i < 4; i++) {
29 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_A53 + i * 4, ~0x0);
30 mmio_write_32(IMX_GPC_BASE + IMR1_CORE1_A53 + i * 4, ~0x0);
31 mmio_write_32(IMX_GPC_BASE + IMR1_CORE2_A53 + i * 4, ~0x0);
32 mmio_write_32(IMX_GPC_BASE + IMR1_CORE3_A53 + i * 4, ~0x0);
33 mmio_write_32(IMX_GPC_BASE + IMR1_CORE0_M4 + i * 4, ~0x0);
34 }
35
36 val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);
37 /* use GIC wake_request to wakeup C0~C3 from LPM */
38 val |= 0x30c00000;
39 /* clear the MASTER0 LPM handshake */
40 val &= ~(1 << 6);
41 mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);
42
43 /* clear MASTER1 & MASTER2 mapping in CPU0(A53) */
44 mmio_clrbits_32(IMX_GPC_BASE + MST_CPU_MAPPING, (MASTER1_MAPPING |
45 MASTER2_MAPPING));
46
47 /* set all mix/PU in A53 domain */
48 mmio_write_32(IMX_GPC_BASE + PGC_CPU_0_1_MAPPING, 0xffff);
49
50 /*
51 * Set the CORE & SCU power up timing:
52 * SW = 0x1, SW2ISO = 0x1;
53 * the CPU CORE and SCU power up timming counter
54 * is drived by 32K OSC, each domain's power up
55 * latency is (SW + SW2ISO) / 32768
56 */
57 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(0) + 0x4, 0x81);
58 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(1) + 0x4, 0x81);
59 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(2) + 0x4, 0x81);
60 mmio_write_32(IMX_GPC_BASE + COREx_PGC_PCR(3) + 0x4, 0x81);
61 mmio_write_32(IMX_GPC_BASE + PLAT_PGC_PCR + 0x4, 0x81);
62 mmio_write_32(IMX_GPC_BASE + PGC_SCU_TIMING,
63 (0x59 << 10) | 0x5B | (0x2 << 20));
64
65 /* set DUMMY PDN/PUP ACK by default for A53 domain */
66 mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53,
67 A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK);
68
69 /* clear DSM by default */
70 val = mmio_read_32(IMX_GPC_BASE + SLPCR);
71 val &= ~SLPCR_EN_DSM;
72 /* enable the fast wakeup wait mode */
73 val |= SLPCR_A53_FASTWUP_WAIT_MODE;
74 /* clear the RBC */
75 val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT);
76 /* set the STBY_COUNT to 0x5, (128 * 30)us */
77 val &= ~(0x7 << SLPCR_STBY_COUNT_SHFT);
78 val |= (0x5 << SLPCR_STBY_COUNT_SHFT);
79 mmio_write_32(IMX_GPC_BASE + SLPCR, val);
80
81 /*
82 * USB PHY power up needs to make sure RESET bit in SRC is clear,
83 * otherwise, the PU power up bit in GPC will NOT self-cleared.
84 * only need to do it once.
85 */
86 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
87 mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
88
89 /* enable all the power domain by default */
90 mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x3fcf);
91 }
92