1 /*
2 * Copyright 2017-2021 NXP
3 * Copyright 2021 Arm
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9
10 #include <arch_helpers.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <common/desc_image_load.h>
14 #include <context.h>
15 #include <drivers/console.h>
16 #include <drivers/generic_delay_timer.h>
17 #include <drivers/mmc.h>
18 #include <lib/mmio.h>
19 #include <lib/optee_utils.h>
20 #include <lib/utils.h>
21 #include <stdbool.h>
22 #include <tbbr_img_def.h>
23
24 #include <imx_aipstz.h>
25 #include <imx_csu.h>
26 #include <imx_uart.h>
27 #include <imx_usdhc.h>
28 #include <plat/common/platform.h>
29
30 #include "imx8mm_private.h"
31 #include "platform_def.h"
32
33 static const struct aipstz_cfg aipstz[] = {
34 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
35 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
36 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
37 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
38 {0},
39 };
40
imx8mm_usdhc_setup(void)41 static void imx8mm_usdhc_setup(void)
42 {
43 imx_usdhc_params_t params;
44 struct mmc_device_info info;
45
46 params.reg_base = PLAT_IMX8MM_BOOT_MMC_BASE;
47 /*
48 The imx8mm SD Card Speed modes for USDHC2
49 +--------------+--------------------+--------------+--------------+
50 |Bus Speed Mode|Max. Clock Frequency|Max. Bus Speed|Signal Voltage|
51 +--------------+--------------------+--------------+--------------+
52 |Default Speed | 25 MHz | 12.5 MB/s | 3.3V |
53 |High Speed | 50 MHz | 25 MB/s | 3.3V |
54 +--------------+--------------------+--------------+--------------+
55
56 We pick 50 Mhz here for High Speed access.
57 */
58 params.clk_rate = 50000000;
59 params.bus_width = MMC_BUS_WIDTH_1;
60 params.flags = 0;
61 info.mmc_dev_type = MMC_IS_SD;
62 info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
63 imx_usdhc_init(¶ms, &info);
64 }
65
bl2_el3_early_platform_setup(u_register_t arg1,u_register_t arg2,u_register_t arg3,u_register_t arg4)66 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
67 u_register_t arg3, u_register_t arg4)
68 {
69 int i;
70 static console_t console;
71
72 /* enable CSU NS access permission */
73 for (i = 0; i < MAX_CSU_NUM; i++) {
74 mmio_write_32(IMX_CSU_BASE + i * 4, CSU_CSL_OPEN_ACCESS);
75 }
76
77 /* config the aips access permission */
78 imx_aipstz_init(aipstz);
79
80 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
81 IMX_CONSOLE_BAUDRATE, &console);
82
83 generic_delay_timer_init();
84
85 /* select the CKIL source to 32K OSC */
86 mmio_write_32(0x30360124, 0x1);
87
88 imx8mm_usdhc_setup();
89
90 /* Open handles to a FIP image */
91 plat_imx_io_setup();
92 }
93
bl2_el3_plat_arch_setup(void)94 void bl2_el3_plat_arch_setup(void)
95 {
96 }
97
bl2_platform_setup(void)98 void bl2_platform_setup(void)
99 {
100 }
101
bl2_plat_handle_post_image_load(unsigned int image_id)102 int bl2_plat_handle_post_image_load(unsigned int image_id)
103 {
104 int err = 0;
105 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
106 bl_mem_params_node_t *pager_mem_params = NULL;
107 bl_mem_params_node_t *paged_mem_params = NULL;
108
109 assert(bl_mem_params);
110
111 switch (image_id) {
112 case BL32_IMAGE_ID:
113 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
114 assert(pager_mem_params);
115
116 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
117 assert(paged_mem_params);
118
119 err = parse_optee_header(&bl_mem_params->ep_info,
120 &pager_mem_params->image_info,
121 &paged_mem_params->image_info);
122 if (err != 0) {
123 WARN("OPTEE header parse error.\n");
124 }
125
126 break;
127 default:
128 /* Do nothing in default case */
129 break;
130 }
131
132 return err;
133 }
134
plat_get_syscnt_freq2(void)135 unsigned int plat_get_syscnt_freq2(void)
136 {
137 return COUNTER_FREQUENCY;
138 }
139
bl2_plat_runtime_setup(void)140 void bl2_plat_runtime_setup(void)
141 {
142 return;
143 }
144