1 /*
2  * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <arch.h>
8 #include <common/tbbr/tbbr_img_def.h>
9 
10 #define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
11 #define PLATFORM_LINKER_ARCH		aarch64
12 
13 #define PLATFORM_STACK_SIZE		0xB00
14 #define CACHE_WRITEBACK_GRANULE		64
15 
16 #define PLAT_PRIMARY_CPU		U(0x0)
17 #define PLATFORM_MAX_CPU_PER_CLUSTER	U(4)
18 #define PLATFORM_CLUSTER_COUNT		U(1)
19 #define PLATFORM_CLUSTER0_CORE_COUNT	U(4)
20 #define PLATFORM_CLUSTER1_CORE_COUNT	U(0)
21 #define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER0_CORE_COUNT)
22 
23 #define IMX_PWR_LVL0			MPIDR_AFFLVL0
24 #define IMX_PWR_LVL1			MPIDR_AFFLVL1
25 #define IMX_PWR_LVL2			MPIDR_AFFLVL2
26 
27 #define PWR_DOMAIN_AT_MAX_LVL		U(1)
28 #define PLAT_MAX_PWR_LVL		U(2)
29 #define PLAT_MAX_OFF_STATE		U(4)
30 #define PLAT_MAX_RET_STATE		U(2)
31 
32 #define PLAT_WAIT_RET_STATE		U(1)
33 #define PLAT_STOP_OFF_STATE		U(3)
34 
35 #define PLAT_PRI_BITS			U(3)
36 #define PLAT_SDEI_CRITICAL_PRI		0x10
37 #define PLAT_SDEI_NORMAL_PRI		0x20
38 #define PLAT_SDEI_SGI_PRIVATE		U(9)
39 
40 #if defined(NEED_BL2)
41 #define BL2_BASE			U(0x920000)
42 #define BL2_LIMIT			U(0x940000)
43 #define BL31_BASE			U(0x900000)
44 #define BL31_LIMIT			U(0x920000)
45 #define IMX_FIP_BASE			U(0x40310000)
46 #define IMX_FIP_SIZE			U(0x000300000)
47 #define IMX_FIP_LIMIT			U(FIP_BASE + FIP_SIZE)
48 
49 /* Define FIP image location on eMMC */
50 #define IMX_FIP_MMC_BASE		U(0x100000)
51 
52 #define PLAT_IMX8MM_BOOT_MMC_BASE	U(0x30B50000) /* SD */
53 #else
54 #define BL31_BASE			U(0x920000)
55 #define BL31_LIMIT			U(0x940000)
56 #endif
57 
58 /* non-secure uboot base */
59 #define PLAT_NS_IMAGE_OFFSET		U(0x40200000)
60 #define PLAT_NS_IMAGE_SIZE		U(0x00200000)
61 
62 /* GICv3 base address */
63 #define PLAT_GICD_BASE			U(0x38800000)
64 #define PLAT_GICR_BASE			U(0x38880000)
65 
66 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 32)
67 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 32)
68 
69 #define MAX_XLAT_TABLES			8
70 #define MAX_MMAP_REGIONS		16
71 
72 #define HAB_RVT_BASE			U(0x00000900) /* HAB_RVT for i.MX8MM */
73 
74 #define IMX_BOOT_UART_CLK_IN_HZ		24000000 /* Select 24MHz oscillator */
75 
76 #define PLAT_CRASH_UART_BASE		IMX_BOOT_UART_BASE
77 #define PLAT_CRASH_UART_CLK_IN_HZ	24000000
78 #define IMX_CONSOLE_BAUDRATE		115200
79 
80 #define IMX_AIPSTZ1			U(0x301f0000)
81 #define IMX_AIPSTZ2			U(0x305f0000)
82 #define IMX_AIPSTZ3			U(0x309f0000)
83 #define IMX_AIPSTZ4			U(0x32df0000)
84 
85 #define IMX_AIPS_BASE			U(0x30000000)
86 #define IMX_AIPS_SIZE			U(0xC00000)
87 #define IMX_GPV_BASE			U(0x32000000)
88 #define IMX_GPV_SIZE			U(0x800000)
89 #define IMX_AIPS1_BASE			U(0x30200000)
90 #define IMX_AIPS4_BASE			U(0x32c00000)
91 #define IMX_ANAMIX_BASE			U(0x30360000)
92 #define IMX_CCM_BASE			U(0x30380000)
93 #define IMX_SRC_BASE			U(0x30390000)
94 #define IMX_GPC_BASE			U(0x303a0000)
95 #define IMX_RDC_BASE			U(0x303d0000)
96 #define IMX_CSU_BASE			U(0x303e0000)
97 #define IMX_WDOG_BASE			U(0x30280000)
98 #define IMX_SNVS_BASE			U(0x30370000)
99 #define IMX_NOC_BASE			U(0x32700000)
100 #define IMX_TZASC_BASE			U(0x32F80000)
101 #define IMX_IOMUX_GPR_BASE		U(0x30340000)
102 #define IMX_CAAM_BASE			U(0x30900000)
103 #define IMX_DDRC_BASE			U(0x3d400000)
104 #define IMX_DDRPHY_BASE			U(0x3c000000)
105 #define IMX_DDR_IPS_BASE		U(0x3d000000)
106 #define IMX_ROM_BASE			U(0x0)
107 
108 #define GPV_BASE			U(0x32000000)
109 #define GPV_SIZE			U(0x800000)
110 #define IMX_GIC_BASE			PLAT_GICD_BASE
111 #define IMX_GIC_SIZE			U(0x200000)
112 
113 #define WDOG_WSR			U(0x2)
114 #define WDOG_WCR_WDZST			BIT(0)
115 #define WDOG_WCR_WDBG			BIT(1)
116 #define WDOG_WCR_WDE			BIT(2)
117 #define WDOG_WCR_WDT			BIT(3)
118 #define WDOG_WCR_SRS			BIT(4)
119 #define WDOG_WCR_WDA			BIT(5)
120 #define WDOG_WCR_SRE			BIT(6)
121 #define WDOG_WCR_WDW			BIT(7)
122 
123 #define SRC_A53RCR0			U(0x4)
124 #define SRC_A53RCR1			U(0x8)
125 #define SRC_OTG1PHY_SCR			U(0x20)
126 #define SRC_OTG2PHY_SCR			U(0x24)
127 #define SRC_GPR1_OFFSET			U(0x74)
128 #define SRC_GPR10_OFFSET		U(0x98)
129 #define SRC_GPR10_PERSIST_SECONDARY_BOOT	BIT(30)
130 
131 #define SNVS_LPCR			U(0x38)
132 #define SNVS_LPCR_SRTC_ENV		BIT(0)
133 #define SNVS_LPCR_DP_EN			BIT(5)
134 #define SNVS_LPCR_TOP			BIT(6)
135 
136 #define IOMUXC_GPR10			U(0x28)
137 #define GPR_TZASC_EN			BIT(0)
138 #define GPR_TZASC_EN_LOCK		BIT(16)
139 
140 #define ANAMIX_MISC_CTL			U(0x124)
141 
142 #define MAX_CSU_NUM			U(64)
143 
144 #define OCRAM_S_BASE			U(0x00180000)
145 #define OCRAM_S_SIZE			U(0x8000)
146 #define OCRAM_S_LIMIT			(OCRAM_S_BASE + OCRAM_S_SIZE)
147 
148 #define COUNTER_FREQUENCY		8000000 /* 8MHz */
149 
150 #define IMX_WDOG_B_RESET
151 
152 #define MAX_IO_HANDLES			3U
153 #define MAX_IO_DEVICES			2U
154 #define MAX_IO_BLOCK_DEVICES		1U
155