1 /*
2  * Copyright 2019-2020 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <stdbool.h>
9 
10 #include <arch_helpers.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <context.h>
14 #include <drivers/arm/tzc380.h>
15 #include <drivers/console.h>
16 #include <drivers/generic_delay_timer.h>
17 #include <lib/el3_runtime/context_mgmt.h>
18 #include <lib/mmio.h>
19 #include <lib/xlat_tables/xlat_tables_v2.h>
20 #include <plat/common/platform.h>
21 
22 #include <gpc.h>
23 #include <imx_aipstz.h>
24 #include <imx_uart.h>
25 #include <imx_rdc.h>
26 #include <imx8m_caam.h>
27 #include <platform_def.h>
28 #include <plat_imx8.h>
29 
30 static const mmap_region_t imx_mmap[] = {
31 	GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP, {0},
32 };
33 
34 static const struct aipstz_cfg aipstz[] = {
35 	{IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
36 	{IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
37 	{IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
38 	{IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
39 	{0},
40 };
41 
42 static const struct imx_rdc_cfg rdc[] = {
43 	/* Master domain assignment */
44 	RDC_MDAn(0x1, DID1),
45 
46 	/* peripherals domain permission */
47 
48 	/* memory region */
49 	RDC_MEM_REGIONn(16, 0x0, 0x0, 0xff),
50 	RDC_MEM_REGIONn(17, 0x0, 0x0, 0xff),
51 	RDC_MEM_REGIONn(18, 0x0, 0x0, 0xff),
52 
53 	/* Sentinel */
54 	{0},
55 };
56 
57 static entry_point_info_t bl32_image_ep_info;
58 static entry_point_info_t bl33_image_ep_info;
59 
60 /* get SPSR for BL33 entry */
get_spsr_for_bl33_entry(void)61 static uint32_t get_spsr_for_bl33_entry(void)
62 {
63 	unsigned long el_status;
64 	unsigned long mode;
65 	uint32_t spsr;
66 
67 	/* figure out what mode we enter the non-secure world */
68 	el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
69 	el_status &= ID_AA64PFR0_ELX_MASK;
70 
71 	mode = (el_status) ? MODE_EL2 : MODE_EL1;
72 
73 	spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
74 	return spsr;
75 }
76 
bl31_tzc380_setup(void)77 static void bl31_tzc380_setup(void)
78 {
79 	unsigned int val;
80 
81 	val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
82 	if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
83 		return;
84 
85 	tzc380_init(IMX_TZASC_BASE);
86 
87 	/*
88 	 * Need to substact offset 0x40000000 from CPU address when
89 	 * programming tzasc region for i.mx8mn.
90 	 */
91 
92 	/* Enable 1G-5G S/NS RW */
93 	tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
94 		TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
95 }
96 
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)97 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
98 		u_register_t arg2, u_register_t arg3)
99 {
100 	static console_t console;
101 	int i;
102 
103 	/* Enable CSU NS access permission */
104 	for (i = 0; i < 64; i++) {
105 		mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
106 	}
107 
108 	imx_aipstz_init(aipstz);
109 
110 	imx_rdc_init(rdc);
111 
112 	imx8m_caam_init();
113 
114 	console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
115 		IMX_CONSOLE_BAUDRATE, &console);
116 	/* This console is only used for boot stage */
117 	console_set_scope(&console, CONSOLE_FLAG_BOOT);
118 
119 	/*
120 	 * tell BL3-1 where the non-secure software image is located
121 	 * and the entry state information.
122 	 */
123 	bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
124 	bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
125 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
126 
127 #ifdef SPD_opteed
128 	/* Populate entry point information for BL32 */
129 	SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
130 	SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
131 	bl32_image_ep_info.pc = BL32_BASE;
132 	bl32_image_ep_info.spsr = 0;
133 
134 	/* Pass TEE base and size to bl33 */
135 	bl33_image_ep_info.args.arg1 = BL32_BASE;
136 	bl33_image_ep_info.args.arg2 = BL32_SIZE;
137 #endif
138 
139 	bl31_tzc380_setup();
140 }
141 
bl31_plat_arch_setup(void)142 void bl31_plat_arch_setup(void)
143 {
144 	mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE),
145 		MT_MEMORY | MT_RW | MT_SECURE);
146 	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE),
147 		MT_MEMORY | MT_RO | MT_SECURE);
148 #if USE_COHERENT_MEM
149 	mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
150 		(BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE),
151 		MT_DEVICE | MT_RW | MT_SECURE);
152 #endif
153 	mmap_add(imx_mmap);
154 
155 	init_xlat_tables();
156 
157 	enable_mmu_el3(0);
158 }
159 
bl31_platform_setup(void)160 void bl31_platform_setup(void)
161 {
162 	generic_delay_timer_init();
163 
164 	/* select the CKIL source to 32K OSC */
165 	mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
166 
167 	plat_gic_driver_init();
168 	plat_gic_init();
169 
170 	imx_gpc_init();
171 }
172 
bl31_plat_get_next_image_ep_info(unsigned int type)173 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
174 {
175 	if (type == NON_SECURE)
176 		return &bl33_image_ep_info;
177 	if (type == SECURE)
178 		return &bl32_image_ep_info;
179 
180 	return NULL;
181 }
182 
plat_get_syscnt_freq2(void)183 unsigned int plat_get_syscnt_freq2(void)
184 {
185 	return COUNTER_FREQUENCY;
186 }
187