1 /*
2 * Copyright 2020 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9
10 #include <arch_helpers.h>
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <context.h>
14 #include <drivers/arm/tzc380.h>
15 #include <drivers/console.h>
16 #include <drivers/generic_delay_timer.h>
17 #include <lib/el3_runtime/context_mgmt.h>
18 #include <lib/mmio.h>
19 #include <lib/xlat_tables/xlat_tables_v2.h>
20 #include <plat/common/platform.h>
21
22 #include <gpc.h>
23 #include <imx_aipstz.h>
24 #include <imx_uart.h>
25 #include <imx_rdc.h>
26 #include <imx8m_caam.h>
27 #include <platform_def.h>
28 #include <plat_imx8.h>
29
30 static const mmap_region_t imx_mmap[] = {
31 GIC_MAP, AIPS_MAP, OCRAM_S_MAP, DDRC_MAP,
32 NOC_MAP, {0},
33 };
34
35 static const struct aipstz_cfg aipstz[] = {
36 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
37 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
38 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
39 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
40 {0},
41 };
42
43 static const struct imx_rdc_cfg rdc[] = {
44 /* Master domain assignment */
45 RDC_MDAn(0x1, DID1),
46
47 /* peripherals domain permission */
48
49 /* memory region */
50
51 /* Sentinel */
52 {0},
53 };
54
55 static entry_point_info_t bl32_image_ep_info;
56 static entry_point_info_t bl33_image_ep_info;
57
58 /* get SPSR for BL33 entry */
get_spsr_for_bl33_entry(void)59 static uint32_t get_spsr_for_bl33_entry(void)
60 {
61 unsigned long el_status;
62 unsigned long mode;
63 uint32_t spsr;
64
65 /* figure out what mode we enter the non-secure world */
66 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
67 el_status &= ID_AA64PFR0_ELX_MASK;
68
69 mode = (el_status) ? MODE_EL2 : MODE_EL1;
70
71 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
72 return spsr;
73 }
74
bl31_tzc380_setup(void)75 static void bl31_tzc380_setup(void)
76 {
77 unsigned int val;
78
79 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
80 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
81 return;
82
83 tzc380_init(IMX_TZASC_BASE);
84
85 /*
86 * Need to substact offset 0x40000000 from CPU address when
87 * programming tzasc region for i.mx8mp.
88 */
89
90 /* Enable 1G-5G S/NS RW */
91 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
92 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
93 }
94
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)95 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
96 u_register_t arg2, u_register_t arg3)
97 {
98 static console_t console;
99 unsigned int i;
100
101 /* Enable CSU NS access permission */
102 for (i = 0; i < 64; i++) {
103 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
104 }
105
106 imx_aipstz_init(aipstz);
107
108 imx_rdc_init(rdc);
109
110 imx8m_caam_init();
111
112 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
113 IMX_CONSOLE_BAUDRATE, &console);
114 /* This console is only used for boot stage */
115 console_set_scope(&console, CONSOLE_FLAG_BOOT);
116
117 /*
118 * tell BL3-1 where the non-secure software image is located
119 * and the entry state information.
120 */
121 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
122 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
123 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
124
125 #ifdef SPD_opteed
126 /* Populate entry point information for BL32 */
127 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
128 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
129 bl32_image_ep_info.pc = BL32_BASE;
130 bl32_image_ep_info.spsr = 0;
131
132 /* Pass TEE base and size to bl33 */
133 bl33_image_ep_info.args.arg1 = BL32_BASE;
134 bl33_image_ep_info.args.arg2 = BL32_SIZE;
135 #endif
136
137 bl31_tzc380_setup();
138 }
139
bl31_plat_arch_setup(void)140 void bl31_plat_arch_setup(void)
141 {
142 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE),
143 MT_MEMORY | MT_RW | MT_SECURE);
144 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE),
145 MT_MEMORY | MT_RO | MT_SECURE);
146 #if USE_COHERENT_MEM
147 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
148 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE),
149 MT_DEVICE | MT_RW | MT_SECURE);
150 #endif
151 mmap_add(imx_mmap);
152
153 init_xlat_tables();
154
155 enable_mmu_el3(0);
156 }
157
bl31_platform_setup(void)158 void bl31_platform_setup(void)
159 {
160 generic_delay_timer_init();
161
162 /* select the CKIL source to 32K OSC */
163 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
164
165 plat_gic_driver_init();
166 plat_gic_init();
167
168 imx_gpc_init();
169 }
170
bl31_plat_get_next_image_ep_info(unsigned int type)171 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
172 {
173 if (type == NON_SECURE) {
174 return &bl33_image_ep_info;
175 }
176
177 if (type == SECURE) {
178 return &bl32_image_ep_info;
179 }
180
181 return NULL;
182 }
183
plat_get_syscnt_freq2(void)184 unsigned int plat_get_syscnt_freq2(void)
185 {
186 return COUNTER_FREQUENCY;
187 }
188