1 /*
2  * Copyright 2020 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef GPC_REG_H
8 #define GPC_REG_H
9 
10 #define LPCR_A53_BSC			0x0
11 #define LPCR_A53_BSC2			0x180
12 #define LPCR_A53_AD			0x4
13 #define LPCR_M4				0x8
14 #define SLPCR				0x14
15 #define MST_CPU_MAPPING			0x18
16 #define MLPCR				0x20
17 #define PGC_ACK_SEL_A53			0x24
18 #define IMR1_CORE0_A53			0x30
19 #define IMR1_CORE1_A53			0x44
20 #define IMR1_CORE2_A53			0x194
21 #define IMR1_CORE3_A53			0x1A8
22 #define IMR1_CORE0_M4			0x58
23 
24 #define SLT0_CFG			0x200
25 #define GPC_PU_PWRHSK			0x190
26 #define PGC_CPU_0_1_MAPPING		0x1CC
27 #define CPU_PGC_UP_TRG			0xD0
28 #define PU_PGC_UP_TRG			0xD8
29 #define CPU_PGC_DN_TRG			0xDC
30 #define PU_PGC_DN_TRG			0xE4
31 #define LPS_CPU1			0xEC
32 
33 #define A53_CORE0_PGC			0x800
34 #define A53_PLAT_PGC			0x900
35 #define PLAT_PGC_PCR			0x900
36 #define NOC_PGC_PCR			0xa40
37 #define PGC_SCU_TIMING			0x910
38 
39 #define MASK_DSM_TRIGGER_A53		BIT(31)
40 #define IRQ_SRC_A53_WUP			BIT(30)
41 #define IRQ_SRC_A53_WUP_SHIFT		30
42 #define IRQ_SRC_C1			BIT(29)
43 #define IRQ_SRC_C0			BIT(28)
44 #define IRQ_SRC_C3			BIT(23)
45 #define IRQ_SRC_C2			BIT(22)
46 #define CPU_CLOCK_ON_LPM		BIT(14)
47 #define A53_CLK_ON_LPM			BIT(14)
48 #define MASTER0_LPM_HSK			BIT(6)
49 #define MASTER1_LPM_HSK			BIT(7)
50 #define MASTER2_LPM_HSK			BIT(8)
51 
52 #define L2PGE				BIT(31)
53 #define EN_L2_WFI_PDN			BIT(5)
54 #define EN_PLAT_PDN			BIT(4)
55 
56 #define SLPCR_EN_DSM			BIT(31)
57 #define SLPCR_RBC_EN			BIT(30)
58 #define SLPCR_A53_FASTWUP_STOP_MODE	BIT(17)
59 #define SLPCR_A53_FASTWUP_WAIT_MODE	BIT(16)
60 #define SLPCR_VSTBY			BIT(2)
61 #define SLPCR_SBYOS			BIT(1)
62 #define SLPCR_BYPASS_PMIC_READY		BIT(0)
63 #define SLPCR_RBC_COUNT_SHIFT		24
64 #define SLPCR_STBY_COUNT_SHFT		3
65 
66 #define A53_DUMMY_PDN_ACK		BIT(30)
67 #define A53_DUMMY_PUP_ACK		BIT(31)
68 #define A53_PLAT_PDN_ACK		BIT(8)
69 #define A53_PLAT_PUP_ACK		BIT(9)
70 
71 #define NOC_PDN_SLT_CTRL		BIT(12)
72 #define NOC_PUP_SLT_CTRL		BIT(13)
73 #define NOC_PGC_PDN_ACK			BIT(12)
74 #define NOC_PGC_PUP_ACK			BIT(13)
75 
76 #define PLAT_PUP_SLT_CTRL		BIT(9)
77 #define PLAT_PDN_SLT_CTRL		BIT(8)
78 
79 #define SLT_PLAT_PDN			BIT(8)
80 #define SLT_PLAT_PUP			BIT(9)
81 
82 #define MASTER1_MAPPING			BIT(1)
83 #define MASTER2_MAPPING			BIT(2)
84 
85 #define TMR_TCD2_SHIFT			0
86 #define TMC_TMR_SHIFT			10
87 #define TRC1_TMC_SHIFT			20
88 
89 #define MIPI_PHY1_PWR_REQ		BIT(0)
90 #define PCIE_PHY_PWR_REQ		BIT(1)
91 #define USB1_PHY_PWR_REQ		BIT(2)
92 #define USB2_PHY_PWR_REQ		BIT(3)
93 #define MLMIX_PWR_REQ			BIT(4)
94 #define AUDIOMIX_PWR_REQ		BIT(5)
95 #define GPU2D_PWR_REQ			BIT(6)
96 #define GPUMIX_PWR_REQ			BIT(7)
97 #define VPUMIX_PWR_REQ			BIT(8)
98 #define GPU3D_PWR_REQ			BIT(9)
99 #define MEDIAMIX_PWR_REQ		BIT(10)
100 #define VPU_G1_PWR_REQ			BIT(11)
101 #define VPU_G2_PWR_REQ			BIT(12)
102 #define VPU_H1_PWR_REQ			BIT(13)
103 #define HDMIMIX_PWR_REQ			BIT(14)
104 #define HDMI_PHY_PWR_REQ		BIT(15)
105 #define MIPI_PHY2_PWR_REQ		BIT(16)
106 #define HSIOMIX_PWR_REQ			BIT(17)
107 #define MEDIAMIX_ISPDWP_PWR_REQ		BIT(18)
108 #define DDRMIX_PWR_REQ			BIT(19)
109 
110 #define AUDIOMIX_ADB400_SYNC		(BIT(4) | BIT(15))
111 #define MLMIX_ADB400_SYNC		(BIT(7) | BIT(8))
112 #define GPUMIX_ADB400_SYNC		BIT(9)
113 #define VPUMIX_ADB400_SYNC		BIT(10)
114 #define DDRMIX_ADB400_SYNC		BIT(11)
115 #define HSIOMIX_ADB400_SYNC		BIT(12)
116 #define HDMIMIX_ADB400_SYNC		BIT(13)
117 #define MEDIAMIX_ADB400_SYNC		BIT(14)
118 
119 #define AUDIOMIX_ADB400_ACK		(BIT(20) | BIT(31))
120 #define MLMIX_ADB400_ACK		(BIT(23) | BIT(24))
121 #define GPUMIX_ADB400_ACK		BIT(25)
122 #define VPUMIX_ADB400_ACK		BIT(26)
123 #define DDRMIX_ADB400_ACK		BIT(27)
124 #define HSIOMIX_ADB400_ACK		BIT(28)
125 #define HDMIMIX_ADB400_ACK		BIT(29)
126 #define MEDIAMIX_ADB400_ACK		BIT(30)
127 
128 #define MIPI_PHY1_PGC			0xb00
129 #define PCIE_PHY_PGC			0xb40
130 #define USB1_PHY_PGC			0xb80
131 #define USB2_PHY_PGC			0xbc0
132 #define MLMIX_PGC			0xc00
133 #define AUDIOMIX_PGC			0xc40
134 #define GPU2D_PGC			0xc80
135 #define GPUMIX_PGC			0xcc0
136 #define VPUMIX_PGC			0xd00
137 #define GPU3D_PGC			0xd40
138 #define MEDIAMIX_PGC			0xd80
139 #define VPU_G1_PGC			0xdc0
140 #define VPU_G2_PGC			0xe00
141 #define VPU_H1_PGC			0xe40
142 #define HDMIMIX_PGC			0xe80
143 #define HDMI_PHY_PGC			0xec0
144 #define MIPI_PHY2_PGC			0xf00
145 #define HSIOMIX_PGC			0xf40
146 #define MEDIAMIX_ISPDWP_PGC		0xf80
147 #define DDRMIX_PGC			0xfc0
148 
149 #define IRQ_IMR_NUM			U(5)
150 
151 #endif /* GPC_REG_H */
152