1/*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <cpu_macros.S>
10#include <platform_def.h>
11#include <el3_common_macros.S>
12
13	.globl	plat_secondary_cold_boot_setup
14	.globl	platform_is_primary_cpu
15	.globl	plat_is_my_cpu_primary
16	.globl	plat_my_core_pos
17	.globl	plat_crash_console_init
18	.globl	plat_crash_console_putc
19	.globl  plat_crash_console_flush
20	.globl	platform_mem_init
21	.globl	plat_secondary_cpus_bl31_entry
22
23	.globl plat_get_my_entrypoint
24
25	/* -----------------------------------------------------
26	 * void plat_secondary_cold_boot_setup (void);
27	 *
28	 * This function performs any platform specific actions
29	 * needed for a secondary cpu after a cold reset e.g
30	 * mark the cpu's presence, mechanism to place it in a
31	 * holding pen etc.
32	 * -----------------------------------------------------
33	 */
34func plat_secondary_cold_boot_setup
35	/* Wait until the it gets reset signal from rstmgr gets populated */
36poll_mailbox:
37	wfi
38	mov_imm	x0, PLAT_SEC_ENTRY
39	ldr	x1, [x0]
40	mov_imm	x2, PLAT_CPUID_RELEASE
41	ldr	x3, [x2]
42	mrs	x4, mpidr_el1
43	and	x4, x4, #0xff
44	cmp	x3, x4
45	b.ne	poll_mailbox
46	br	x1
47endfunc plat_secondary_cold_boot_setup
48
49func platform_is_primary_cpu
50	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
51	cmp	x0, #PLAT_PRIMARY_CPU
52	cset	x0, eq
53	ret
54endfunc platform_is_primary_cpu
55
56func plat_is_my_cpu_primary
57	mrs	x0, mpidr_el1
58	b   platform_is_primary_cpu
59endfunc plat_is_my_cpu_primary
60
61func plat_my_core_pos
62	mrs	x0, mpidr_el1
63	and	x1, x0, #MPIDR_CPU_MASK
64	and	x0, x0, #MPIDR_CLUSTER_MASK
65	add	x0, x1, x0, LSR #6
66	ret
67endfunc plat_my_core_pos
68
69func warm_reset_req
70	str	xzr, [x4]
71	bl	plat_is_my_cpu_primary
72	cbz	x0, cpu_in_wfi
73	mov_imm x1, PLAT_SEC_ENTRY
74	str	xzr, [x1]
75	mrs	x1, rmr_el3
76	orr	x1, x1, #0x02
77	msr	rmr_el3, x1
78	isb
79	dsb	sy
80cpu_in_wfi:
81	wfi
82	b	cpu_in_wfi
83endfunc warm_reset_req
84
85func plat_get_my_entrypoint
86	ldr	x4, =L2_RESET_DONE_REG
87	ldr	x5, [x4]
88	ldr	x1, =L2_RESET_DONE_STATUS
89	cmp	x1, x5
90	b.eq	warm_reset_req
91	mov_imm	x1, PLAT_SEC_ENTRY
92	ldr	x0, [x1]
93	ret
94endfunc plat_get_my_entrypoint
95
96
97	/* ---------------------------------------------
98	 * int plat_crash_console_init(void)
99	 * Function to initialize the crash console
100	 * without a C Runtime to print crash report.
101	 * Clobber list : x0, x1, x2
102	 * ---------------------------------------------
103	 */
104func plat_crash_console_init
105	mov_imm	x0, PLAT_UART0_BASE
106	mov_imm	x1, PLAT_UART_CLOCK
107	mov_imm	x2, PLAT_BAUDRATE
108	b	console_16550_core_init
109endfunc plat_crash_console_init
110
111	/* ---------------------------------------------
112	 * int plat_crash_console_putc(void)
113	 * Function to print a character on the crash
114	 * console without a C Runtime.
115	 * Clobber list : x1, x2
116	 * ---------------------------------------------
117	 */
118func plat_crash_console_putc
119	mov_imm x1, PLAT_UART0_BASE
120	b	console_16550_core_putc
121endfunc plat_crash_console_putc
122
123func plat_crash_console_flush
124	mov_imm x0, CRASH_CONSOLE_BASE
125	b	console_16550_core_flush
126endfunc plat_crash_console_flush
127
128
129	/* --------------------------------------------------------
130	 * void platform_mem_init (void);
131	 *
132	 * Any memory init, relocation to be done before the
133	 * platform boots. Called very early in the boot process.
134	 * --------------------------------------------------------
135	 */
136func platform_mem_init
137	mov	x0, #0
138	ret
139endfunc platform_mem_init
140
141func plat_secondary_cpus_bl31_entry
142	el3_entrypoint_common                                   \
143		_init_sctlr=0                                   \
144		_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS  \
145		_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU      \
146		_init_memory=1                                  \
147		_init_c_runtime=1                               \
148		_exception_vectors=runtime_exceptions		\
149		_pie_fixup_size=BL31_LIMIT - BL31_BASE
150endfunc plat_secondary_cpus_bl31_entry
151