1 /*
2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <common/debug.h>
9 #include <common/runtime_svc.h>
10 #include <lib/mmio.h>
11 #include <tools_share/uuid.h>
12
13 #include "socfpga_mailbox.h"
14 #include "socfpga_reset_manager.h"
15 #include "socfpga_sip_svc.h"
16
17
18 /* Total buffer the driver can hold */
19 #define FPGA_CONFIG_BUFFER_SIZE 4
20
21 static int current_block, current_buffer;
22 static int read_block, max_blocks, is_partial_reconfig;
23 static uint32_t send_id, rcv_id;
24 static uint32_t bytes_per_block, blocks_submitted;
25
26
27 /* SiP Service UUID */
28 DEFINE_SVC_UUID2(intl_svc_uid,
29 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a,
30 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81);
31
socfpga_sip_handler(uint32_t smc_fid,uint64_t x1,uint64_t x2,uint64_t x3,uint64_t x4,void * cookie,void * handle,uint64_t flags)32 static uint64_t socfpga_sip_handler(uint32_t smc_fid,
33 uint64_t x1,
34 uint64_t x2,
35 uint64_t x3,
36 uint64_t x4,
37 void *cookie,
38 void *handle,
39 uint64_t flags)
40 {
41 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
42 SMC_RET1(handle, SMC_UNK);
43 }
44
45 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
46
intel_fpga_sdm_write_buffer(struct fpga_config_info * buffer)47 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
48 {
49 uint32_t args[3];
50
51 while (max_blocks > 0 && buffer->size > buffer->size_written) {
52 args[0] = (1<<8);
53 args[1] = buffer->addr + buffer->size_written;
54 if (buffer->size - buffer->size_written <= bytes_per_block) {
55 args[2] = buffer->size - buffer->size_written;
56 current_buffer++;
57 current_buffer %= FPGA_CONFIG_BUFFER_SIZE;
58 } else
59 args[2] = bytes_per_block;
60
61 buffer->size_written += args[2];
62 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args,
63 3U, CMD_INDIRECT);
64
65 buffer->subblocks_sent++;
66 max_blocks--;
67 }
68
69 return !max_blocks;
70 }
71
intel_fpga_sdm_write_all(void)72 static int intel_fpga_sdm_write_all(void)
73 {
74 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
75 if (intel_fpga_sdm_write_buffer(
76 &fpga_config_buffers[current_buffer]))
77 break;
78 return 0;
79 }
80
intel_mailbox_fpga_config_isdone(uint32_t query_type)81 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type)
82 {
83 uint32_t ret;
84
85 if (query_type == 1)
86 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS);
87 else
88 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS);
89
90 if (ret) {
91 if (ret == MBOX_CFGSTAT_STATE_CONFIG)
92 return INTEL_SIP_SMC_STATUS_BUSY;
93 else
94 return INTEL_SIP_SMC_STATUS_ERROR;
95 }
96
97 if (query_type != 1) {
98 /* full reconfiguration */
99 if (!is_partial_reconfig)
100 socfpga_bridges_enable(); /* Enable bridge */
101 }
102
103 return INTEL_SIP_SMC_STATUS_OK;
104 }
105
mark_last_buffer_xfer_completed(uint32_t * buffer_addr_completed)106 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed)
107 {
108 int i;
109
110 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
111 if (fpga_config_buffers[i].block_number == current_block) {
112 fpga_config_buffers[i].subblocks_sent--;
113 if (fpga_config_buffers[i].subblocks_sent == 0
114 && fpga_config_buffers[i].size <=
115 fpga_config_buffers[i].size_written) {
116 fpga_config_buffers[i].write_requested = 0;
117 current_block++;
118 *buffer_addr_completed =
119 fpga_config_buffers[i].addr;
120 return 0;
121 }
122 }
123 }
124
125 return -1;
126 }
127
intel_fpga_config_completed_write(uint32_t * completed_addr,uint32_t * count,uint32_t * job_id)128 static int intel_fpga_config_completed_write(uint32_t *completed_addr,
129 uint32_t *count, uint32_t *job_id)
130 {
131 uint32_t status = INTEL_SIP_SMC_STATUS_OK;
132 *count = 0;
133 int resp_len = 0;
134 uint32_t resp[5];
135 int all_completed = 1;
136
137 while (*count < 3) {
138
139 resp_len = mailbox_read_response(job_id,
140 resp, ARRAY_SIZE(resp));
141
142 if (resp_len < 0)
143 break;
144
145 max_blocks++;
146
147 if (mark_last_buffer_xfer_completed(
148 &completed_addr[*count]) == 0)
149 *count = *count + 1;
150 else
151 break;
152 }
153
154 if (*count <= 0) {
155 if (resp_len != MBOX_NO_RESPONSE &&
156 resp_len != MBOX_TIMEOUT && resp_len != 0) {
157 mailbox_clear_response();
158 return INTEL_SIP_SMC_STATUS_ERROR;
159 }
160
161 *count = 0;
162 }
163
164 intel_fpga_sdm_write_all();
165
166 if (*count > 0)
167 status = INTEL_SIP_SMC_STATUS_OK;
168 else if (*count == 0)
169 status = INTEL_SIP_SMC_STATUS_BUSY;
170
171 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
172 if (fpga_config_buffers[i].write_requested != 0) {
173 all_completed = 0;
174 break;
175 }
176 }
177
178 if (all_completed == 1)
179 return INTEL_SIP_SMC_STATUS_OK;
180
181 return status;
182 }
183
intel_fpga_config_start(uint32_t config_type)184 static int intel_fpga_config_start(uint32_t config_type)
185 {
186 uint32_t response[3];
187 int status = 0;
188
189 is_partial_reconfig = config_type;
190
191 mailbox_clear_response();
192
193 mailbox_send_cmd(1U, MBOX_CMD_CANCEL, NULL, 0U, CMD_CASUAL, NULL, 0U);
194
195 status = mailbox_send_cmd(1U, MBOX_RECONFIG, NULL, 0U, CMD_CASUAL,
196 response, ARRAY_SIZE(response));
197
198 if (status < 0)
199 return status;
200
201 max_blocks = response[0];
202 bytes_per_block = response[1];
203
204 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
205 fpga_config_buffers[i].size = 0;
206 fpga_config_buffers[i].size_written = 0;
207 fpga_config_buffers[i].addr = 0;
208 fpga_config_buffers[i].write_requested = 0;
209 fpga_config_buffers[i].block_number = 0;
210 fpga_config_buffers[i].subblocks_sent = 0;
211 }
212
213 blocks_submitted = 0;
214 current_block = 0;
215 read_block = 0;
216 current_buffer = 0;
217
218 /* full reconfiguration */
219 if (!is_partial_reconfig) {
220 /* Disable bridge */
221 socfpga_bridges_disable();
222 }
223
224 return 0;
225 }
226
is_fpga_config_buffer_full(void)227 static bool is_fpga_config_buffer_full(void)
228 {
229 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++)
230 if (!fpga_config_buffers[i].write_requested)
231 return false;
232 return true;
233 }
234
is_address_in_ddr_range(uint64_t addr,uint64_t size)235 bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
236 {
237 if (size > (UINT64_MAX - addr))
238 return false;
239 if (addr < BL31_LIMIT)
240 return false;
241 if (addr + size > DRAM_BASE + DRAM_SIZE)
242 return false;
243
244 return true;
245 }
246
intel_fpga_config_write(uint64_t mem,uint64_t size)247 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size)
248 {
249 int i;
250
251 intel_fpga_sdm_write_all();
252
253 if (!is_address_in_ddr_range(mem, size) ||
254 is_fpga_config_buffer_full())
255 return INTEL_SIP_SMC_STATUS_REJECTED;
256
257 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) {
258 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE;
259
260 if (!fpga_config_buffers[j].write_requested) {
261 fpga_config_buffers[j].addr = mem;
262 fpga_config_buffers[j].size = size;
263 fpga_config_buffers[j].size_written = 0;
264 fpga_config_buffers[j].write_requested = 1;
265 fpga_config_buffers[j].block_number =
266 blocks_submitted++;
267 fpga_config_buffers[j].subblocks_sent = 0;
268 break;
269 }
270 }
271
272 if (is_fpga_config_buffer_full())
273 return INTEL_SIP_SMC_STATUS_BUSY;
274
275 return INTEL_SIP_SMC_STATUS_OK;
276 }
277
is_out_of_sec_range(uint64_t reg_addr)278 static int is_out_of_sec_range(uint64_t reg_addr)
279 {
280 switch (reg_addr) {
281 case(0xF8011100): /* ECCCTRL1 */
282 case(0xF8011104): /* ECCCTRL2 */
283 case(0xF8011110): /* ERRINTEN */
284 case(0xF8011114): /* ERRINTENS */
285 case(0xF8011118): /* ERRINTENR */
286 case(0xF801111C): /* INTMODE */
287 case(0xF8011120): /* INTSTAT */
288 case(0xF8011124): /* DIAGINTTEST */
289 case(0xF801112C): /* DERRADDRA */
290 case(0xFFD12028): /* SDMMCGRP_CTRL */
291 case(0xFFD12044): /* EMAC0 */
292 case(0xFFD12048): /* EMAC1 */
293 case(0xFFD1204C): /* EMAC2 */
294 case(0xFFD12090): /* ECC_INT_MASK_VALUE */
295 case(0xFFD12094): /* ECC_INT_MASK_SET */
296 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */
297 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */
298 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */
299 case(0xFFD120C0): /* NOC_TIMEOUT */
300 case(0xFFD120C4): /* NOC_IDLEREQ_SET */
301 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */
302 case(0xFFD120D0): /* NOC_IDLEACK */
303 case(0xFFD120D4): /* NOC_IDLESTATUS */
304 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */
305 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */
306 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */
307 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */
308 return 0;
309
310 default:
311 break;
312 }
313
314 return -1;
315 }
316
317 /* Secure register access */
intel_secure_reg_read(uint64_t reg_addr,uint32_t * retval)318 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval)
319 {
320 if (is_out_of_sec_range(reg_addr))
321 return INTEL_SIP_SMC_STATUS_ERROR;
322
323 *retval = mmio_read_32(reg_addr);
324
325 return INTEL_SIP_SMC_STATUS_OK;
326 }
327
intel_secure_reg_write(uint64_t reg_addr,uint32_t val,uint32_t * retval)328 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val,
329 uint32_t *retval)
330 {
331 if (is_out_of_sec_range(reg_addr))
332 return INTEL_SIP_SMC_STATUS_ERROR;
333
334 mmio_write_32(reg_addr, val);
335
336 return intel_secure_reg_read(reg_addr, retval);
337 }
338
intel_secure_reg_update(uint64_t reg_addr,uint32_t mask,uint32_t val,uint32_t * retval)339 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
340 uint32_t val, uint32_t *retval)
341 {
342 if (!intel_secure_reg_read(reg_addr, retval)) {
343 *retval &= ~mask;
344 *retval |= val;
345 return intel_secure_reg_write(reg_addr, *retval, retval);
346 }
347
348 return INTEL_SIP_SMC_STATUS_ERROR;
349 }
350
351 /* Intel Remote System Update (RSU) services */
352 uint64_t intel_rsu_update_address;
353
intel_rsu_status(uint64_t * respbuf,unsigned int respbuf_sz)354 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz)
355 {
356 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0)
357 return INTEL_SIP_SMC_RSU_ERROR;
358
359 return INTEL_SIP_SMC_STATUS_OK;
360 }
361
intel_rsu_update(uint64_t update_address)362 static uint32_t intel_rsu_update(uint64_t update_address)
363 {
364 intel_rsu_update_address = update_address;
365 return INTEL_SIP_SMC_STATUS_OK;
366 }
367
intel_rsu_notify(uint32_t execution_stage)368 static uint32_t intel_rsu_notify(uint32_t execution_stage)
369 {
370 if (mailbox_hps_stage_notify(execution_stage) < 0)
371 return INTEL_SIP_SMC_RSU_ERROR;
372
373 return INTEL_SIP_SMC_STATUS_OK;
374 }
375
intel_rsu_retry_counter(uint32_t * respbuf,uint32_t respbuf_sz,uint32_t * ret_stat)376 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
377 uint32_t *ret_stat)
378 {
379 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0)
380 return INTEL_SIP_SMC_RSU_ERROR;
381
382 *ret_stat = respbuf[8];
383 return INTEL_SIP_SMC_STATUS_OK;
384 }
385
386 /* Mailbox services */
intel_mbox_send_cmd(uint32_t cmd,uint32_t * args,uint32_t len,uint32_t urgent,uint32_t * response,uint32_t resp_len,int * mbox_status,int * len_in_resp)387 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, uint32_t len,
388 uint32_t urgent, uint32_t *response,
389 uint32_t resp_len, int *mbox_status,
390 int *len_in_resp)
391 {
392 *len_in_resp = 0;
393 *mbox_status = 0;
394
395 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len))
396 return INTEL_SIP_SMC_STATUS_REJECTED;
397
398 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent,
399 response, resp_len);
400
401 if (status < 0) {
402 *mbox_status = -status;
403 return INTEL_SIP_SMC_STATUS_ERROR;
404 }
405
406 *mbox_status = 0;
407 *len_in_resp = status;
408 return INTEL_SIP_SMC_STATUS_OK;
409 }
410
411 /*
412 * This function is responsible for handling all SiP calls from the NS world
413 */
414
sip_smc_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,u_register_t flags)415 uintptr_t sip_smc_handler(uint32_t smc_fid,
416 u_register_t x1,
417 u_register_t x2,
418 u_register_t x3,
419 u_register_t x4,
420 void *cookie,
421 void *handle,
422 u_register_t flags)
423 {
424 uint32_t retval = 0;
425 uint32_t status = INTEL_SIP_SMC_STATUS_OK;
426 uint32_t completed_addr[3];
427 uint64_t rsu_respbuf[9];
428 u_register_t x5, x6;
429 int mbox_status, len_in_resp;
430
431
432 switch (smc_fid) {
433 case SIP_SVC_UID:
434 /* Return UID to the caller */
435 SMC_UUID_RET(handle, intl_svc_uid);
436
437 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
438 status = intel_mailbox_fpga_config_isdone(x1);
439 SMC_RET4(handle, status, 0, 0, 0);
440
441 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
442 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
443 INTEL_SIP_SMC_FPGA_CONFIG_ADDR,
444 INTEL_SIP_SMC_FPGA_CONFIG_SIZE -
445 INTEL_SIP_SMC_FPGA_CONFIG_ADDR);
446
447 case INTEL_SIP_SMC_FPGA_CONFIG_START:
448 status = intel_fpga_config_start(x1);
449 SMC_RET4(handle, status, 0, 0, 0);
450
451 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE:
452 status = intel_fpga_config_write(x1, x2);
453 SMC_RET4(handle, status, 0, 0, 0);
454
455 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE:
456 status = intel_fpga_config_completed_write(completed_addr,
457 &retval, &rcv_id);
458 switch (retval) {
459 case 1:
460 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
461 completed_addr[0], 0, 0);
462
463 case 2:
464 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
465 completed_addr[0],
466 completed_addr[1], 0);
467
468 case 3:
469 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK,
470 completed_addr[0],
471 completed_addr[1],
472 completed_addr[2]);
473
474 case 0:
475 SMC_RET4(handle, status, 0, 0, 0);
476
477 default:
478 mailbox_clear_response();
479 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
480 }
481
482 case INTEL_SIP_SMC_REG_READ:
483 status = intel_secure_reg_read(x1, &retval);
484 SMC_RET3(handle, status, retval, x1);
485
486 case INTEL_SIP_SMC_REG_WRITE:
487 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
488 SMC_RET3(handle, status, retval, x1);
489
490 case INTEL_SIP_SMC_REG_UPDATE:
491 status = intel_secure_reg_update(x1, (uint32_t)x2,
492 (uint32_t)x3, &retval);
493 SMC_RET3(handle, status, retval, x1);
494
495 case INTEL_SIP_SMC_RSU_STATUS:
496 status = intel_rsu_status(rsu_respbuf,
497 ARRAY_SIZE(rsu_respbuf));
498 if (status) {
499 SMC_RET1(handle, status);
500 } else {
501 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1],
502 rsu_respbuf[2], rsu_respbuf[3]);
503 }
504
505 case INTEL_SIP_SMC_RSU_UPDATE:
506 status = intel_rsu_update(x1);
507 SMC_RET1(handle, status);
508
509 case INTEL_SIP_SMC_RSU_NOTIFY:
510 status = intel_rsu_notify(x1);
511 SMC_RET1(handle, status);
512
513 case INTEL_SIP_SMC_RSU_RETRY_COUNTER:
514 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
515 ARRAY_SIZE(rsu_respbuf), &retval);
516 if (status) {
517 SMC_RET1(handle, status);
518 } else {
519 SMC_RET2(handle, status, retval);
520 }
521
522 case INTEL_SIP_SMC_MBOX_SEND_CMD:
523 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
524 x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
525 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4,
526 (uint32_t *)x5, x6, &mbox_status,
527 &len_in_resp);
528 SMC_RET4(handle, status, mbox_status, x5, len_in_resp);
529
530 default:
531 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
532 cookie, handle, flags);
533 }
534 }
535
536 DECLARE_RT_SVC(
537 socfpga_sip_svc,
538 OEN_SIP_START,
539 OEN_SIP_END,
540 SMC_TYPE_FAST,
541 NULL,
542 sip_smc_handler
543 );
544
545 DECLARE_RT_SVC(
546 socfpga_sip_svc_std,
547 OEN_SIP_START,
548 OEN_SIP_END,
549 SMC_TYPE_YIELD,
550 NULL,
551 sip_smc_handler
552 );
553