1 /*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <arch_helpers.h>
13 #include <common/debug.h>
14 #include <lib/mmio.h>
15 #include <lib/xlat_tables/xlat_tables_v2.h>
16
17 const mmap_region_t *plat_ls_get_mmap(void);
18
19 /*
20 * Table of memory regions for various BL stages to map using the MMU.
21 * This doesn't include Trusted SRAM as ls_setup_page_tables() already
22 * takes care of mapping it.
23 *
24 * The flash needs to be mapped as writable in order to erase the FIP's Table of
25 * Contents in case of unrecoverable error (see plat_error_handler()).
26 */
27 #ifdef IMAGE_BL1
28 const mmap_region_t plat_ls_mmap[] = {
29 LS_MAP_FLASH0_RW,
30 LS_MAP_NS_DRAM,
31 LS_MAP_CCSR,
32 {0}
33 };
34 #endif
35 #ifdef IMAGE_BL2
36 const mmap_region_t plat_ls_mmap[] = {
37 LS_MAP_FLASH0_RW,
38 LS_MAP_CCSR,
39 LS_MAP_NS_DRAM,
40 LS_MAP_TSP_SEC_MEM,
41 {0}
42 };
43 #endif
44 #ifdef IMAGE_BL31
45 const mmap_region_t plat_ls_mmap[] = {
46 LS_MAP_CCSR,
47 LS_MAP_FLASH0_RW,
48 LS_MAP_NS_DRAM,
49 LS_MAP_TSP_SEC_MEM,
50 {0}
51 };
52 #endif
53 #ifdef IMAGE_BL32
54 const mmap_region_t plat_ls_mmap[] = {
55 LS_MAP_CCSR,
56 LS_MAP_FLASH0_RW,
57 LS_MAP_TSP_SEC_MEM,
58 {0}
59 };
60 #endif
61 /*
62 * Set up the page tables for the generic and platform-specific memory regions.
63 * The extents of the generic memory regions are specified by the function
64 * arguments and consist of:
65 * - Trusted SRAM seen by the BL image;
66 * - Code section;
67 * - Read-only data section;
68 * - Coherent memory region, if applicable.
69 */
ls_setup_page_tables(uintptr_t total_base,size_t total_size,uintptr_t code_start,uintptr_t code_limit,uintptr_t rodata_start,uintptr_t rodata_limit,uintptr_t coh_start,uintptr_t coh_limit)70 void ls_setup_page_tables(uintptr_t total_base,
71 size_t total_size,
72 uintptr_t code_start,
73 uintptr_t code_limit,
74 uintptr_t rodata_start,
75 uintptr_t rodata_limit
76 #if USE_COHERENT_MEM
77 ,
78 uintptr_t coh_start,
79 uintptr_t coh_limit
80 #endif
81 )
82 {
83 /* Now (re-)map the platform-specific memory regions */
84 mmap_add(plat_ls_get_mmap());
85 /*
86 * Map the Trusted SRAM with appropriate memory attributes.
87 * Subsequent mappings will adjust the attributes for specific regions.
88 */
89 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
90 (void *) total_base, (void *) (total_base + total_size));
91 mmap_add_region(total_base, total_base,
92 total_size,
93 MT_MEMORY | MT_RW | MT_SECURE);
94
95 /* Re-map the code section */
96 VERBOSE("Code region: %p - %p\n",
97 (void *) code_start, (void *) code_limit);
98 mmap_add_region(code_start, code_start,
99 code_limit - code_start,
100 MT_CODE | MT_SECURE);
101
102 /* Re-map the read-only data section */
103 VERBOSE("Read-only data region: %p - %p\n",
104 (void *) rodata_start, (void *) rodata_limit);
105 mmap_add_region(rodata_start, rodata_start,
106 rodata_limit - rodata_start,
107 MT_RO_DATA | MT_SECURE);
108
109 #if USE_COHERENT_MEM
110 /* Re-map the coherent memory region */
111 VERBOSE("Coherent region: %p - %p\n",
112 (void *) coh_start, (void *) coh_limit);
113 mmap_add_region(coh_start, coh_start,
114 coh_limit - coh_start,
115 MT_DEVICE | MT_RW | MT_SECURE);
116 #endif
117
118 /* Create the page tables to reflect the above mappings */
119 init_xlat_tables();
120 }
121
plat_get_ns_image_entrypoint(void)122 uintptr_t plat_get_ns_image_entrypoint(void)
123 {
124 #ifdef PRELOADED_BL33_BASE
125 return PRELOADED_BL33_BASE;
126 #else
127 return LS_NS_DRAM_BASE;
128 #endif
129 }
130
131 /*******************************************************************************
132 * Gets SPSR for BL32 entry
133 ******************************************************************************/
ls_get_spsr_for_bl32_entry(void)134 uint32_t ls_get_spsr_for_bl32_entry(void)
135 {
136 /*
137 * The Secure Payload Dispatcher service is responsible for
138 * setting the SPSR prior to entry into the BL32 image.
139 */
140 return 0;
141 }
142
143 /*******************************************************************************
144 * Gets SPSR for BL33 entry
145 ******************************************************************************/
146 #ifdef __aarch64__
ls_get_spsr_for_bl33_entry(void)147 uint32_t ls_get_spsr_for_bl33_entry(void)
148 {
149 unsigned int mode;
150 uint32_t spsr;
151
152 /* Figure out what mode we enter the non-secure world in */
153 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
154
155 /*
156 * TODO: Consider the possibility of specifying the SPSR in
157 * the FIP ToC and allowing the platform to have a say as
158 * well.
159 */
160 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
161 return spsr;
162 }
163 #else
164 /*******************************************************************************
165 * Gets SPSR for BL33 entry
166 ******************************************************************************/
ls_get_spsr_for_bl33_entry(void)167 uint32_t ls_get_spsr_for_bl33_entry(void)
168 {
169 unsigned int hyp_status, mode, spsr;
170
171 hyp_status = GET_VIRT_EXT(read_id_pfr1());
172
173 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
174
175 /*
176 * TODO: Consider the possibility of specifying the SPSR in
177 * the FIP ToC and allowing the platform to have a say as
178 * well.
179 */
180 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
181 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
182 return spsr;
183 }
184 #endif /* __aarch64__ */
185
186 /*******************************************************************************
187 * Returns Layerscape platform specific memory map regions.
188 ******************************************************************************/
plat_ls_get_mmap(void)189 const mmap_region_t *plat_ls_get_mmap(void)
190 {
191 return plat_ls_mmap;
192 }
193
194
plat_get_syscnt_freq2(void)195 unsigned int plat_get_syscnt_freq2(void)
196 {
197 unsigned int counter_base_frequency;
198
199 counter_base_frequency = COUNTER_FREQUENCY;
200
201 return counter_base_frequency;
202 }
203