1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SPM_H 8 #define SPM_H 9 10 #define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000) 11 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010) 12 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014) 13 #define SPM_CLK_SETTLE (SPM_BASE + 0x100) 14 #define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218) 15 #define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c) 16 #define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220) 17 #define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264) 18 #define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c) 19 #define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274) 20 #define SPM_MD32_SRAM_CON (SPM_BASE + 0x2c8) 21 #define SPM_PCM_CON0 (SPM_BASE + 0x310) 22 #define SPM_PCM_CON1 (SPM_BASE + 0x314) 23 #define SPM_PCM_IM_PTR (SPM_BASE + 0x318) 24 #define SPM_PCM_IM_LEN (SPM_BASE + 0x31c) 25 #define SPM_PCM_REG_DATA_INI (SPM_BASE + 0x320) 26 #define SPM_PCM_EVENT_VECTOR0 (SPM_BASE + 0x340) 27 #define SPM_PCM_EVENT_VECTOR1 (SPM_BASE + 0x344) 28 #define SPM_PCM_EVENT_VECTOR2 (SPM_BASE + 0x348) 29 #define SPM_PCM_EVENT_VECTOR3 (SPM_BASE + 0x34c) 30 #define SPM_PCM_MAS_PAUSE_MASK (SPM_BASE + 0x354) 31 #define SPM_PCM_PWR_IO_EN (SPM_BASE + 0x358) 32 #define SPM_PCM_TIMER_VAL (SPM_BASE + 0x35c) 33 #define SPM_PCM_TIMER_OUT (SPM_BASE + 0x360) 34 #define SPM_PCM_REG0_DATA (SPM_BASE + 0x380) 35 #define SPM_PCM_REG1_DATA (SPM_BASE + 0x384) 36 #define SPM_PCM_REG2_DATA (SPM_BASE + 0x388) 37 #define SPM_PCM_REG3_DATA (SPM_BASE + 0x38c) 38 #define SPM_PCM_REG4_DATA (SPM_BASE + 0x390) 39 #define SPM_PCM_REG5_DATA (SPM_BASE + 0x394) 40 #define SPM_PCM_REG6_DATA (SPM_BASE + 0x398) 41 #define SPM_PCM_REG7_DATA (SPM_BASE + 0x39c) 42 #define SPM_PCM_REG8_DATA (SPM_BASE + 0x3a0) 43 #define SPM_PCM_REG9_DATA (SPM_BASE + 0x3a4) 44 #define SPM_PCM_REG10_DATA (SPM_BASE + 0x3a8) 45 #define SPM_PCM_REG11_DATA (SPM_BASE + 0x3ac) 46 #define SPM_PCM_REG12_DATA (SPM_BASE + 0x3b0) 47 #define SPM_PCM_REG13_DATA (SPM_BASE + 0x3b4) 48 #define SPM_PCM_REG14_DATA (SPM_BASE + 0x3b8) 49 #define SPM_PCM_REG15_DATA (SPM_BASE + 0x3bc) 50 #define SPM_PCM_EVENT_REG_STA (SPM_BASE + 0x3c0) 51 #define SPM_PCM_FSM_STA (SPM_BASE + 0x3c4) 52 #define SPM_PCM_IM_HOST_RW_PTR (SPM_BASE + 0x3c8) 53 #define SPM_PCM_IM_HOST_RW_DAT (SPM_BASE + 0x3cc) 54 #define SPM_PCM_EVENT_VECTOR4 (SPM_BASE + 0x3d0) 55 #define SPM_PCM_EVENT_VECTOR5 (SPM_BASE + 0x3d4) 56 #define SPM_PCM_EVENT_VECTOR6 (SPM_BASE + 0x3d8) 57 #define SPM_PCM_EVENT_VECTOR7 (SPM_BASE + 0x3dc) 58 #define SPM_PCM_SW_INT_SET (SPM_BASE + 0x3e0) 59 #define SPM_PCM_SW_INT_CLEAR (SPM_BASE + 0x3e4) 60 #define SPM_CLK_CON (SPM_BASE + 0x400) 61 #define SPM_SLEEP_PTPOD2_CON (SPM_BASE + 0x408) 62 #define SPM_APMCU_PWRCTL (SPM_BASE + 0x600) 63 #define SPM_AP_DVFS_CON_SET (SPM_BASE + 0x604) 64 #define SPM_AP_STANBY_CON (SPM_BASE + 0x608) 65 #define SPM_PWR_STATUS (SPM_BASE + 0x60c) 66 #define SPM_PWR_STATUS_2ND (SPM_BASE + 0x610) 67 #define SPM_AP_BSI_REQ (SPM_BASE + 0x614) 68 #define SPM_SLEEP_TIMER_STA (SPM_BASE + 0x720) 69 #define SPM_SLEEP_WAKEUP_EVENT_MASK (SPM_BASE + 0x810) 70 #define SPM_SLEEP_CPU_WAKEUP_EVENT (SPM_BASE + 0x814) 71 #define SPM_SLEEP_MD32_WAKEUP_EVENT_MASK (SPM_BASE + 0x818) 72 #define SPM_PCM_WDT_TIMER_VAL (SPM_BASE + 0x824) 73 #define SPM_PCM_WDT_TIMER_OUT (SPM_BASE + 0x828) 74 #define SPM_PCM_MD32_MAILBOX (SPM_BASE + 0x830) 75 #define SPM_PCM_MD32_IRQ (SPM_BASE + 0x834) 76 #define SPM_SLEEP_ISR_MASK (SPM_BASE + 0x900) 77 #define SPM_SLEEP_ISR_STATUS (SPM_BASE + 0x904) 78 #define SPM_SLEEP_ISR_RAW_STA (SPM_BASE + 0x910) 79 #define SPM_SLEEP_MD32_ISR_RAW_STA (SPM_BASE + 0x914) 80 #define SPM_SLEEP_WAKEUP_MISC (SPM_BASE + 0x918) 81 #define SPM_SLEEP_BUS_PROTECT_RDY (SPM_BASE + 0x91c) 82 #define SPM_SLEEP_SUBSYS_IDLE_STA (SPM_BASE + 0x920) 83 #define SPM_PCM_RESERVE (SPM_BASE + 0xb00) 84 #define SPM_PCM_RESERVE2 (SPM_BASE + 0xb04) 85 #define SPM_PCM_FLAGS (SPM_BASE + 0xb08) 86 #define SPM_PCM_SRC_REQ (SPM_BASE + 0xb0c) 87 #define SPM_PCM_DEBUG_CON (SPM_BASE + 0xb20) 88 #define SPM_CA7_CPU0_IRQ_MASK (SPM_BASE + 0xb30) 89 #define SPM_CA7_CPU1_IRQ_MASK (SPM_BASE + 0xb34) 90 #define SPM_CA7_CPU2_IRQ_MASK (SPM_BASE + 0xb38) 91 #define SPM_CA7_CPU3_IRQ_MASK (SPM_BASE + 0xb3c) 92 #define SPM_CA15_CPU0_IRQ_MASK (SPM_BASE + 0xb40) 93 #define SPM_CA15_CPU1_IRQ_MASK (SPM_BASE + 0xb44) 94 #define SPM_CA15_CPU2_IRQ_MASK (SPM_BASE + 0xb48) 95 #define SPM_CA15_CPU3_IRQ_MASK (SPM_BASE + 0xb4c) 96 #define SPM_PCM_PASR_DPD_0 (SPM_BASE + 0xb60) 97 #define SPM_PCM_PASR_DPD_1 (SPM_BASE + 0xb64) 98 #define SPM_PCM_PASR_DPD_2 (SPM_BASE + 0xb68) 99 #define SPM_PCM_PASR_DPD_3 (SPM_BASE + 0xb6c) 100 #define SPM_SLEEP_CA7_WFI0_EN (SPM_BASE + 0xf00) 101 #define SPM_SLEEP_CA7_WFI1_EN (SPM_BASE + 0xf04) 102 #define SPM_SLEEP_CA7_WFI2_EN (SPM_BASE + 0xf08) 103 #define SPM_SLEEP_CA7_WFI3_EN (SPM_BASE + 0xf0c) 104 #define SPM_SLEEP_CA15_WFI0_EN (SPM_BASE + 0xf10) 105 #define SPM_SLEEP_CA15_WFI1_EN (SPM_BASE + 0xf14) 106 #define SPM_SLEEP_CA15_WFI2_EN (SPM_BASE + 0xf18) 107 #define SPM_SLEEP_CA15_WFI3_EN (SPM_BASE + 0xf1c) 108 109 #define SPM_PROJECT_CODE 0xb16 110 111 #define SPM_REGWR_EN (1U << 0) 112 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) 113 114 #define SPM_CPU_PDN_DIS (1U << 0) 115 #define SPM_INFRA_PDN_DIS (1U << 1) 116 #define SPM_DDRPHY_PDN_DIS (1U << 2) 117 #define SPM_DUALVCORE_PDN_DIS (1U << 3) 118 #define SPM_PASR_DIS (1U << 4) 119 #define SPM_DPD_DIS (1U << 5) 120 #define SPM_SODI_DIS (1U << 6) 121 #define SPM_MEMPLL_RESET (1U << 7) 122 #define SPM_MAINPLL_PDN_DIS (1U << 8) 123 #define SPM_CPU_DVS_DIS (1U << 9) 124 #define SPM_CPU_DORMANT (1U << 10) 125 #define SPM_EXT_VSEL_GPIO103 (1U << 11) 126 #define SPM_DDR_HIGH_SPEED (1U << 12) 127 #define SPM_OPT (1U << 13) 128 129 #define POWER_ON_VAL1_DEF 0x01011820 130 #define PCM_FSM_STA_DEF 0x48490 131 #define PCM_END_FSM_STA_DEF 0x08490 132 #define PCM_END_FSM_STA_MASK 0x3fff0 133 #define PCM_HANDSHAKE_SEND1 0xbeefbeef 134 135 #define PCM_WDT_TIMEOUT (30 * 32768) 136 #define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) 137 138 #define CON0_PCM_KICK (1U << 0) 139 #define CON0_IM_KICK (1U << 1) 140 #define CON0_IM_SLEEP_DVS (1U << 3) 141 #define CON0_PCM_SW_RESET (1U << 15) 142 #define CON0_CFG_KEY (SPM_PROJECT_CODE << 16) 143 144 #define CON1_IM_SLAVE (1U << 0) 145 #define CON1_MIF_APBEN (1U << 3) 146 #define CON1_PCM_TIMER_EN (1U << 5) 147 #define CON1_IM_NONRP_EN (1U << 6) 148 #define CON1_PCM_WDT_EN (1U << 8) 149 #define CON1_PCM_WDT_WAKE_MODE (1U << 9) 150 #define CON1_SPM_SRAM_SLP_B (1U << 10) 151 #define CON1_SPM_SRAM_ISO_B (1U << 11) 152 #define CON1_EVENT_LOCK_EN (1U << 12) 153 #define CON1_CFG_KEY (SPM_PROJECT_CODE << 16) 154 155 #define PCM_PWRIO_EN_R0 (1U << 0) 156 #define PCM_PWRIO_EN_R7 (1U << 7) 157 #define PCM_RF_SYNC_R0 (1U << 16) 158 #define PCM_RF_SYNC_R2 (1U << 18) 159 #define PCM_RF_SYNC_R6 (1U << 22) 160 #define PCM_RF_SYNC_R7 (1U << 23) 161 162 #define CC_SYSCLK0_EN_0 (1U << 0) 163 #define CC_SYSCLK0_EN_1 (1U << 1) 164 #define CC_SYSCLK1_EN_0 (1U << 2) 165 #define CC_SYSCLK1_EN_1 (1U << 3) 166 #define CC_SYSSETTLE_SEL (1U << 4) 167 #define CC_LOCK_INFRA_DCM (1U << 5) 168 #define CC_SRCLKENA_MASK_0 (1U << 6) 169 #define CC_CXO32K_RM_EN_MD1 (1U << 9) 170 #define CC_CXO32K_RM_EN_MD2 (1U << 10) 171 #define CC_CLKSQ1_SEL (1U << 12) 172 #define CC_DISABLE_DORM_PWR (1U << 14) 173 #define CC_MD32_DCM_EN (1U << 18) 174 175 #define WFI_OP_AND 1 176 #define WFI_OP_OR 0 177 178 #define WAKE_MISC_PCM_TIMER (1U << 19) 179 #define WAKE_MISC_CPU_WAKE (1U << 20) 180 181 /* define WAKE_SRC_XXX */ 182 #define WAKE_SRC_SPM_MERGE (1 << 0) 183 #define WAKE_SRC_KP (1 << 2) 184 #define WAKE_SRC_WDT (1 << 3) 185 #define WAKE_SRC_GPT (1 << 4) 186 #define WAKE_SRC_EINT (1 << 6) 187 #define WAKE_SRC_LOW_BAT (1 << 9) 188 #define WAKE_SRC_MD32 (1 << 10) 189 #define WAKE_SRC_USB_CD (1 << 14) 190 #define WAKE_SRC_USB_PDN (1 << 15) 191 #define WAKE_SRC_AFE (1 << 20) 192 #define WAKE_SRC_THERM (1 << 21) 193 #define WAKE_SRC_SYSPWREQ (1 << 24) 194 #define WAKE_SRC_SEJ (1 << 27) 195 #define WAKE_SRC_ALL_MD32 (1 << 28) 196 #define WAKE_SRC_CPU_IRQ (1 << 29) 197 198 #endif /* SPM_H */ 199