1# 2# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7MTK_PLAT := plat/mediatek 8MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} 9 10# Add OEM customized codes 11OEMS := true 12MTK_SIP_KERNEL_BOOT_ENABLE := 1 13 14 15ifneq (${OEMS},none) 16 OEMS_INCLUDES := -I${MTK_PLAT}/common/custom/ 17 OEMS_SOURCES := ${MTK_PLAT}/common/custom/oem_svc.c 18endif 19 20PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ 21 -I${MTK_PLAT}/common/drivers/uart \ 22 -I${MTK_PLAT_SOC}/ \ 23 -I${MTK_PLAT_SOC}/drivers/timer/ \ 24 -I${MTK_PLAT_SOC}/include/ \ 25 -Iinclude/plat/arm/common/ \ 26 ${OEMS_INCLUDES} 27 28PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \ 29 lib/xlat_tables/xlat_tables_common.c \ 30 plat/common/plat_gic.c 31 32BL31_SOURCES += drivers/arm/cci/cci.c \ 33 drivers/delay_timer/generic_delay_timer.c \ 34 drivers/arm/gic/common/gic_common.c \ 35 drivers/arm/gic/v2/gicv2_main.c \ 36 drivers/arm/gic/v2/gicv2_helpers.c \ 37 plat/common/plat_gicv2.c \ 38 drivers/console/aarch64/console.S \ 39 drivers/delay_timer/delay_timer.c \ 40 lib/cpus/aarch64/cortex_a53.S \ 41 ${MTK_PLAT_SOC}/bl31_plat_setup.c \ 42 ${MTK_PLAT_SOC}/plat_mt_gic.c \ 43 ${MTK_PLAT}/common/mtk_sip_svc.c \ 44 ${MTK_PLAT}/common/mtk_plat_common.c \ 45 ${MTK_PLAT}/common/drivers/uart/8250_console.S \ 46 ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ 47 ${MTK_PLAT_SOC}/drivers/timer/mt_cpuxgpt.c \ 48 ${MTK_PLAT_SOC}/plat_delay_timer.c \ 49 ${MTK_PLAT_SOC}/plat_pm.c \ 50 ${MTK_PLAT_SOC}/plat_topology.c \ 51 ${MTK_PLAT_SOC}/power_tracer.c \ 52 ${MTK_PLAT_SOC}/scu.c \ 53 ${OEMS_SOURCES} 54 55# Enable workarounds for selected Cortex-A53 erratas. 56ERRATA_A53_826319 := 1 57ERRATA_A53_836870 := 1 58 59WORKAROUND_CVE_2017_5715 := 0 60 61# indicate the reset vector address can be programmed 62PROGRAMMABLE_RESET_ADDRESS := 1 63 64$(eval $(call add_define,MTK_SIP_KERNEL_BOOT_ENABLE)) 65 66# Do not enable SVE 67ENABLE_SVE_FOR_NS := 0 68