1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MCSI_H 8 #define MCSI_H 9 10 #define SLAVE_IFACE7_OFFSET 0x1700 11 #define SLAVE_IFACE6_OFFSET 0x1600 12 #define SLAVE_IFACE5_OFFSET 0x1500 13 #define SLAVE_IFACE4_OFFSET 0x1400 14 #define SLAVE_IFACE3_OFFSET 0x1300 15 #define SLAVE_IFACE2_OFFSET 0x1200 16 #define SLAVE_IFACE1_OFFSET 0x1100 17 #define SLAVE_IFACE0_OFFSET 0x1000 18 #define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \ 19 (0x100 * (index))) 20 /* Control and ID register offsets */ 21 #define CENTRAL_CTRL_REG 0x0 22 #define ERR_FLAG_REG 0x4 23 #define SF_INIT_REG 0x10 24 #define SF_CTRL_REG 0x14 25 #define DCM_CTRL_REG 0x18 26 #define ERR_FLAG2_REG 0x20 27 #define SNP_PENDING_REG 0x28 28 #define ACP_PENDING_REG 0x2c 29 #define FLUSH_SF 0x500 30 #define SYS_CCE_CTRL 0x2000 31 #define MST1_CTRL 0x2100 32 #define MTS2_CTRL 0x2200 33 #define XBAR_ARAW_ARB 0x3000 34 #define XBAR_R_ARB 0x3004 35 36 /* Slave interface register offsets */ 37 #define SNOOP_CTRL_REG 0x0 38 #define QOS_CTRL_REG 0x4 39 #define QOS_OVERRIDE_REG 0x8 40 #define QOS_TARGET_REG 0xc 41 #define BD_CTRL_REG 0x40 42 43 /* Snoop Control register bit definitions */ 44 #define DVM_SUPPORT (1U << 31) 45 #define SNP_SUPPORT (1 << 30) 46 #define SHAREABLE_OVWRT (1 << 2) 47 #define DVM_EN_BIT (1 << 1) 48 #define SNOOP_EN_BIT (1 << 0) 49 #define SF2_INIT_DONE (1 << 17) 50 #define SF1_INIT_DONE (1 << 16) 51 #define TRIG_SF2_INIT (1 << 1) 52 #define TRIG_SF1_INIT (1 << 0) 53 54 /* Status register bit definitions */ 55 #define SNP_PENDING 31 56 57 /* Status bit */ 58 #define NS_ACC 1 59 #define S_ACC 0 60 61 /* Central control register bit definitions */ 62 #define PMU_SECURE_ACC_EN (1 << 4) 63 #define INT_EN (1 << 3) 64 #define SECURE_ACC_EN (1 << 2) 65 #define DVM_DIS (1 << 1) 66 #define SNOOP_DIS (1 << 0) 67 68 #define MSCI_MEMORY_SZ (0x10000) 69 70 #define MCSI_REG_ACCESS_READ (0x0) 71 #define MCSI_REG_ACCESS_WRITE (0x1) 72 #define MCSI_REG_ACCESS_SET_BITMASK (0x2) 73 #define MCSI_REG_ACCESS_CLEAR_BITMASK (0x3) 74 75 #define NR_MAX_SLV (7) 76 77 /* ICCS */ 78 #define CACHE_INSTR_EN (1 << 2) 79 #define IDLE_CACHE (1 << 3) 80 #define USE_SHARED_CACHE (1 << 4) 81 #define CACHE_SHARED_PRE_EN (1 << 5) 82 #define CACHE_SHARED_POST_EN (1 << 6) 83 84 #define ACP_PENDING_MASK (0x1007f) 85 86 #define CCI_CLK_CTRL (MCUCFG_BASE + 0x660) 87 88 #ifndef __ASSEMBLER__ 89 90 #include <plat/common/common_def.h> 91 #include <stdint.h> 92 93 /* Function declarations */ 94 95 /* 96 * The MCSI driver must be initialized with the base address of the 97 * MCSI device in the platform memory map, and the cluster indices for 98 * the MCSI slave interfaces 3 and 4 respectively. These are the fully 99 * coherent ACE slave interfaces of MCSI. 100 * The cluster indices must either be 0 or 1, corresponding to the level 1 101 * affinity instance of the mpidr representing the cluster. A negative cluster 102 * index indicates that no cluster is present on that slave interface. 103 */ 104 void mcsi_init(unsigned long cci_base, 105 unsigned int num_cci_masters); 106 void mcsi_cache_flush(void); 107 108 void cci_enable_cluster_coherency(unsigned long mpidr); 109 void cci_disable_cluster_coherency(unsigned long mpidr); 110 111 void cci_secure_switch(unsigned int ns); 112 void cci_init_sf(void); 113 unsigned long cci_reg_access(unsigned int op, unsigned long offset, unsigned long val); 114 115 #endif /* __ASSEMBLER__ */ 116 #endif /* MCSI_H */ 117