1 /* 2 * Copyright (c) 2019, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PMIC_WRAP_INIT_H 8 #define PMIC_WRAP_INIT_H 9 10 #include <platform_def.h> 11 #include <stdint.h> 12 13 /* external API */ 14 int32_t pwrap_read(uint32_t adr, uint32_t *rdata); 15 int32_t pwrap_write(uint32_t adr, uint32_t wdata); 16 17 static struct mt8183_pmic_wrap_regs *const mtk_pwrap = 18 (void *)PMIC_WRAP_BASE; 19 20 /* timeout setting */ 21 enum { 22 TIMEOUT_READ = 255, /* us */ 23 TIMEOUT_WAIT_IDLE = 255 /* us */ 24 }; 25 26 /* PMIC_WRAP registers */ 27 struct mt8183_pmic_wrap_regs { 28 uint32_t reserved[776]; 29 uint32_t wacs2_cmd; 30 uint32_t wacs2_rdata; 31 uint32_t wacs2_vldclr; 32 uint32_t reserved1[4]; 33 }; 34 35 enum { 36 RDATA_WACS_RDATA_SHIFT = 0, 37 RDATA_WACS_FSM_SHIFT = 16, 38 RDATA_WACS_REQ_SHIFT = 19, 39 RDATA_SYNC_IDLE_SHIFT, 40 RDATA_INIT_DONE_SHIFT, 41 RDATA_SYS_IDLE_SHIFT, 42 }; 43 44 enum { 45 RDATA_WACS_RDATA_MASK = 0xffff, 46 RDATA_WACS_FSM_MASK = 0x7, 47 RDATA_WACS_REQ_MASK = 0x1, 48 RDATA_SYNC_IDLE_MASK = 0x1, 49 RDATA_INIT_DONE_MASK = 0x1, 50 RDATA_SYS_IDLE_MASK = 0x1, 51 }; 52 53 /* WACS_FSM */ 54 enum { 55 WACS_FSM_IDLE = 0x00, 56 WACS_FSM_REQ = 0x02, 57 WACS_FSM_WFDLE = 0x04, 58 WACS_FSM_WFVLDCLR = 0x06, 59 WACS_INIT_DONE = 0x01, 60 WACS_SYNC_IDLE = 0x01, 61 WACS_SYNC_BUSY = 0x00 62 }; 63 64 /* error information flag */ 65 enum { 66 E_PWR_INVALID_ARG = 1, 67 E_PWR_INVALID_RW = 2, 68 E_PWR_INVALID_ADDR = 3, 69 E_PWR_INVALID_WDAT = 4, 70 E_PWR_INVALID_OP_MANUAL = 5, 71 E_PWR_NOT_IDLE_STATE = 6, 72 E_PWR_NOT_INIT_DONE = 7, 73 E_PWR_NOT_INIT_DONE_READ = 8, 74 E_PWR_WAIT_IDLE_TIMEOUT = 9, 75 E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, 76 E_PWR_INIT_SIDLY_FAIL = 11, 77 E_PWR_RESET_TIMEOUT = 12, 78 E_PWR_TIMEOUT = 13, 79 E_PWR_INIT_RESET_SPI = 20, 80 E_PWR_INIT_SIDLY = 21, 81 E_PWR_INIT_REG_CLOCK = 22, 82 E_PWR_INIT_ENABLE_PMIC = 23, 83 E_PWR_INIT_DIO = 24, 84 E_PWR_INIT_CIPHER = 25, 85 E_PWR_INIT_WRITE_TEST = 26, 86 E_PWR_INIT_ENABLE_CRC = 27, 87 E_PWR_INIT_ENABLE_DEWRAP = 28, 88 E_PWR_INIT_ENABLE_EVENT = 29, 89 E_PWR_READ_TEST_FAIL = 30, 90 E_PWR_WRITE_TEST_FAIL = 31, 91 E_PWR_SWITCH_DIO = 32 92 }; 93 94 #endif /* PMIC_WRAP_INIT_H */ 95