1 /*
2  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef MT_GIC_V3_H
8 #define MT_GIC_V3_H
9 
10 #include <lib/mmio.h>
11 
12 #define GIC_INT_MASK (MCUCFG_BASE + 0x5e8)
13 #define GIC500_ACTIVE_SEL_SHIFT 3
14 #define GIC500_ACTIVE_SEL_MASK (0x7 << GIC500_ACTIVE_SEL_SHIFT)
15 #define GIC500_ACTIVE_CPU_SHIFT 16
16 #define GIC500_ACTIVE_CPU_MASK (0xff << GIC500_ACTIVE_CPU_SHIFT)
17 
18 #define NR_INT_POL_CTL 20
19 
20 void mt_gic_driver_init(void);
21 void mt_gic_init(void);
22 void mt_gic_set_pending(uint32_t irq);
23 uint32_t mt_gic_get_pending(uint32_t irq);
24 void mt_gic_cpuif_enable(void);
25 void mt_gic_cpuif_disable(void);
26 void mt_gic_rdistif_init(void);
27 void mt_gic_distif_save(void);
28 void mt_gic_distif_restore(void);
29 void mt_gic_rdistif_save(void);
30 void mt_gic_rdistif_restore(void);
31 void mt_gic_sync_dcm_enable(void);
32 void mt_gic_sync_dcm_disable(void);
33 
34 #endif /* MT_GIC_V3_H */
35