1 /*
2 * Copyright (c) 2020, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <common/debug.h>
9
10 #include <mt_lp_rm.h>
11 #include <mt_spm.h>
12 #include <mt_spm_cond.h>
13 #include <mt_spm_constraint.h>
14 #include <mt_spm_conservation.h>
15 #include <mt_spm_idle.h>
16 #include <mt_spm_internal.h>
17 #include <mt_spm_notifier.h>
18 #include <mt_spm_resource_req.h>
19 #include <mt_spm_reg.h>
20 #include <mt_spm_rc_internal.h>
21 #include <mt_spm_suspend.h>
22 #include <plat_pm.h>
23 #include <plat_mtk_lpm.h>
24
25 #define CONSTRAINT_DRAM_ALLOW \
26 (MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
27 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
28 MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
29
30 #define CONSTRAINT_DRAM_PCM_FLAG \
31 (SPM_FLAG_DISABLE_INFRA_PDN | \
32 SPM_FLAG_DISABLE_VCORE_DVS | \
33 SPM_FLAG_DISABLE_VCORE_DFS | \
34 SPM_FLAG_SRAM_SLEEP_CTRL | \
35 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
36
37 #define CONSTRAINT_DRAM_PCM_FLAG1 0U
38
39 #define CONSTRAINT_DRAM_RESOURCE_REQ \
40 (MT_SPM_SYSPLL | \
41 MT_SPM_INFRA | \
42 MT_SPM_26M)
43
44 static struct mt_spm_cond_tables cond_dram = {
45 .name = "dram",
46 .table_cg = {
47 0x078BF1FC, /* MTCMOS1 */
48 0x080D8856, /* INFRA0 */
49 0x03AF9A00, /* INFRA1 */
50 0x86000640, /* INFRA2 */
51 0xC800C000, /* INFRA3 */
52 0x00000000, /* INFRA4 */
53 0x00000000, /* INFRA5 */
54 0x200C0000, /* MMSYS0 */
55 0x00000000, /* MMSYS1 */
56 0x00000000, /* MMSYS2 */
57 },
58 .table_pll = 0U,
59 };
60
61 static struct mt_spm_cond_tables cond_dram_res = {
62 .table_cg = { 0U },
63 .table_pll = 0U,
64 };
65
66 static struct constraint_status status = {
67 .id = MT_RM_CONSTRAINT_ID_DRAM,
68 .valid = (MT_SPM_RC_VALID_SW |
69 MT_SPM_RC_VALID_COND_LATCH |
70 MT_SPM_RC_VALID_XSOC_BBLPM),
71 .cond_block = 0U,
72 .enter_cnt = 0U,
73 .cond_res = &cond_dram_res,
74 };
75
spm_dram_conduct(struct spm_lp_scen * spm_lp,unsigned int * resource_req)76 static void spm_dram_conduct(struct spm_lp_scen *spm_lp,
77 unsigned int *resource_req)
78 {
79 spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
80 spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
81 *resource_req |= CONSTRAINT_DRAM_RESOURCE_REQ;
82 }
83
spm_is_valid_rc_dram(unsigned int cpu,int state_id)84 bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
85 {
86 (void)cpu;
87 (void)state_id;
88
89 return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
90 }
91
spm_update_rc_dram(int state_id,int type,const void * val)92 int spm_update_rc_dram(int state_id, int type, const void *val)
93 {
94 const struct mt_spm_cond_tables *tlb;
95 const struct mt_spm_cond_tables *tlb_check;
96 int res = MT_RM_STATUS_OK;
97
98 if (val == NULL) {
99 return MT_RM_STATUS_BAD;
100 }
101
102 if (type == PLAT_RC_UPDATE_CONDITION) {
103 tlb = (const struct mt_spm_cond_tables *)val;
104 tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
105 status.cond_block =
106 mt_spm_cond_check(state_id, tlb, tlb_check,
107 ((status.valid &
108 MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
109 &cond_dram_res : NULL);
110 } else {
111 res = MT_RM_STATUS_BAD;
112 }
113
114 return res;
115 }
116
spm_allow_rc_dram(int state_id)117 unsigned int spm_allow_rc_dram(int state_id)
118 {
119 (void)state_id;
120
121 return CONSTRAINT_DRAM_ALLOW;
122 }
123
spm_run_rc_dram(unsigned int cpu,int state_id)124 int spm_run_rc_dram(unsigned int cpu, int state_id)
125 {
126 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
127 unsigned int allows = CONSTRAINT_DRAM_ALLOW;
128
129 (void)cpu;
130
131 if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
132 #ifdef MT_SPM_USING_SRCLKEN_RC
133 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
134 #else
135 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
136 #endif
137 }
138
139 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
140 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
141 (IS_PLAT_SUSPEND_ID(state_id) ?
142 MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
143 #else
144 (void)allows;
145 #endif
146
147 if (IS_PLAT_SUSPEND_ID(state_id)) {
148 mt_spm_suspend_enter(state_id,
149 (MT_SPM_EX_OP_SET_WDT |
150 MT_SPM_EX_OP_HW_S1_DETECT),
151 CONSTRAINT_DRAM_RESOURCE_REQ);
152 } else {
153 mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
154 }
155
156 return 0;
157 }
158
spm_reset_rc_dram(unsigned int cpu,int state_id)159 int spm_reset_rc_dram(unsigned int cpu, int state_id)
160 {
161 unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
162 unsigned int allows = CONSTRAINT_DRAM_ALLOW;
163
164 (void)cpu;
165
166 if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
167 #ifdef MT_SPM_USING_SRCLKEN_RC
168 ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
169 #else
170 allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
171 #endif
172 }
173
174 #ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
175 mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
176 #else
177 (void)allows;
178 #endif
179
180 if (IS_PLAT_SUSPEND_ID(state_id)) {
181 mt_spm_suspend_resume(state_id,
182 (MT_SPM_EX_OP_SET_WDT |
183 MT_SPM_EX_OP_HW_S1_DETECT),
184 NULL);
185 } else {
186 mt_spm_idle_generic_resume(state_id, ext_op, NULL);
187 status.enter_cnt++;
188 }
189
190 return 0;
191 }
192