1 /*
2 * Copyright(C)2020, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stddef.h>
8 #include <stdio.h>
9 #include <string.h>
10
11 #include <arch_helpers.h>
12 #include <common/debug.h>
13 #include <drivers/delay_timer.h>
14 #include <lib/mmio.h>
15 #include <plat/common/platform.h>
16 #include <lib/utils_def.h>
17
18 #include <mtk_sip_svc.h>
19 #include <plat_pm.h>
20 #include <platform_def.h>
21
22 #include "mt_spm.h"
23 #include "mt_spm_internal.h"
24 #include "mt_spm_reg.h"
25 #include "mt_spm_vcorefs.h"
26 #include "mt_spm_pmic_wrap.h"
27
28 #define VCORE_CT_ENABLE (1U << 5)
29 #define SW_REQ5_INIT_VAL (6U << 12)
30 #define V_VMODE_SHIFT 0
31 #define VCORE_HV 105
32 #define VCORE_LV 95
33 #define PMIC_STEP_UV 6250
34
35 static const struct reg_config dvfsrc_init_configs[] = {
36 /* Setup opp table */
37 { DVFSRC_LEVEL_LABEL_0_1, 0x50436053 },
38 { DVFSRC_LEVEL_LABEL_2_3, 0x40335042 },
39 { DVFSRC_LEVEL_LABEL_4_5, 0x40314032 },
40 { DVFSRC_LEVEL_LABEL_6_7, 0x30223023 },
41 { DVFSRC_LEVEL_LABEL_8_9, 0x20133021 },
42 { DVFSRC_LEVEL_LABEL_10_11, 0x20112012 },
43 { DVFSRC_LEVEL_LABEL_12_13, 0x10032010 },
44 { DVFSRC_LEVEL_LABEL_14_15, 0x10011002 },
45 { DVFSRC_LEVEL_LABEL_16_17, 0x00131000 },
46 { DVFSRC_LEVEL_LABEL_18_19, 0x00110012 },
47 { DVFSRC_LEVEL_LABEL_20_21, 0x00000010 },
48
49 /* Setup hw emi qos policy */
50 { DVFSRC_DDR_REQUEST, 0x00004321 },
51 { DVFSRC_DDR_REQUEST3, 0x00000065 },
52
53 /* Setup up for PCIe */
54 { DVFSRC_PCIE_VCORE_REQ, 0x0A298001 },
55
56 /* Setup up HRT QOS policy */
57 { DVFSRC_HRT_BW_BASE, 0x00000004 },
58 { DVFSRC_HRT_REQ_UNIT, 0x0000001E },
59 { DVFSRC_HRT_HIGH_3, 0x18A618A6 },
60 { DVFSRC_HRT_HIGH_2, 0x18A61183 },
61 { DVFSRC_HRT_HIGH_1, 0x0D690B80 },
62 { DVFSRC_HRT_HIGH, 0x070804B0 },
63 { DVFSRC_HRT_LOW_3, 0x18A518A5 },
64 { DVFSRC_HRT_LOW_2, 0x18A51182 },
65 { DVFSRC_HRT_LOW_1, 0x0D680B7F },
66 { DVFSRC_HRT_LOW, 0x070704AF },
67 { DVFSRC_HRT_REQUEST, 0x66654321 },
68 /* Setup up SRT QOS policy */
69 { DVFSRC_QOS_EN, 0x0011007C },
70 { DVFSRC_DDR_QOS0, 0x00000019 },
71 { DVFSRC_DDR_QOS1, 0x00000026 },
72 { DVFSRC_DDR_QOS2, 0x00000033 },
73 { DVFSRC_DDR_QOS3, 0x0000003B },
74 { DVFSRC_DDR_QOS4, 0x0000004C },
75 { DVFSRC_DDR_QOS5, 0x00000066 },
76 { DVFSRC_DDR_QOS6, 0x00000066 },
77 { DVFSRC_DDR_REQUEST5, 0x54321000 },
78 { DVFSRC_DDR_REQUEST7, 0x66000000 },
79 /* Setup up hifi request policy */
80 { DVFSRC_DDR_REQUEST6, 0x66543210 },
81 /* Setup up hw request vcore policy */
82 { DVFSRC_VCORE_USER_REQ, 0x00010A29 },
83
84 /* Setup misc*/
85 { DVFSRC_TIMEOUT_NEXTREQ, 0x00000015 },
86 { DVFSRC_RSRV_5, 0x00000001 },
87 { DVFSRC_INT_EN, 0x00000002 },
88 /* Init opp and enable dvfsrc*/
89 { DVFSRC_CURRENT_FORCE, 0x00000001 },
90 { DVFSRC_BASIC_CONTROL, 0x0298444B },
91 { DVFSRC_BASIC_CONTROL, 0x0298054B },
92 { DVFSRC_CURRENT_FORCE, 0x00000000 },
93 };
94
95 static struct pwr_ctrl vcorefs_ctrl = {
96 .wake_src = R12_REG_CPU_WAKEUP,
97
98 /* default VCORE DVFS is disabled */
99 .pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO |
100 SPM_FLAG_DISABLE_VCORE_DVS |
101 SPM_FLAG_DISABLE_VCORE_DFS),
102
103 /* Auto-gen Start */
104
105 /* SPM_AP_STANDBY_CON */
106 .reg_wfi_op = 0,
107 .reg_wfi_type = 0,
108 .reg_mp0_cputop_idle_mask = 0,
109 .reg_mp1_cputop_idle_mask = 0,
110 .reg_mcusys_idle_mask = 0,
111 .reg_md_apsrc_1_sel = 0,
112 .reg_md_apsrc_0_sel = 0,
113 .reg_conn_apsrc_sel = 0,
114
115 /* SPM_SRC_REQ */
116 .reg_spm_apsrc_req = 0,
117 .reg_spm_f26m_req = 0,
118 .reg_spm_infra_req = 0,
119 .reg_spm_vrf18_req = 0,
120 .reg_spm_ddr_en_req = 1,
121 .reg_spm_dvfs_req = 0,
122 .reg_spm_sw_mailbox_req = 0,
123 .reg_spm_sspm_mailbox_req = 0,
124 .reg_spm_adsp_mailbox_req = 0,
125 .reg_spm_scp_mailbox_req = 0,
126
127 /* SPM_SRC6_MASK */
128 .reg_dpmaif_srcclkena_mask_b = 1,
129 .reg_dpmaif_infra_req_mask_b = 1,
130 .reg_dpmaif_apsrc_req_mask_b = 1,
131 .reg_dpmaif_vrf18_req_mask_b = 1,
132 .reg_dpmaif_ddr_en_mask_b = 1,
133
134 /* SPM_SRC_MASK */
135 .reg_md_srcclkena_0_mask_b = 1,
136 .reg_md_srcclkena2infra_req_0_mask_b = 0,
137 .reg_md_apsrc2infra_req_0_mask_b = 1,
138 .reg_md_apsrc_req_0_mask_b = 1,
139 .reg_md_vrf18_req_0_mask_b = 1,
140 .reg_md_ddr_en_0_mask_b = 1,
141 .reg_md_srcclkena_1_mask_b = 0,
142 .reg_md_srcclkena2infra_req_1_mask_b = 0,
143 .reg_md_apsrc2infra_req_1_mask_b = 0,
144 .reg_md_apsrc_req_1_mask_b = 0,
145 .reg_md_vrf18_req_1_mask_b = 0,
146 .reg_md_ddr_en_1_mask_b = 0,
147 .reg_conn_srcclkena_mask_b = 1,
148 .reg_conn_srcclkenb_mask_b = 0,
149 .reg_conn_infra_req_mask_b = 1,
150 .reg_conn_apsrc_req_mask_b = 1,
151 .reg_conn_vrf18_req_mask_b = 1,
152 .reg_conn_ddr_en_mask_b = 1,
153 .reg_conn_vfe28_mask_b = 0,
154 .reg_srcclkeni0_srcclkena_mask_b = 1,
155 .reg_srcclkeni0_infra_req_mask_b = 1,
156 .reg_srcclkeni1_srcclkena_mask_b = 0,
157 .reg_srcclkeni1_infra_req_mask_b = 0,
158 .reg_srcclkeni2_srcclkena_mask_b = 0,
159 .reg_srcclkeni2_infra_req_mask_b = 0,
160 .reg_infrasys_apsrc_req_mask_b = 0,
161 .reg_infrasys_ddr_en_mask_b = 1,
162 .reg_md32_srcclkena_mask_b = 1,
163 .reg_md32_infra_req_mask_b = 1,
164 .reg_md32_apsrc_req_mask_b = 1,
165 .reg_md32_vrf18_req_mask_b = 1,
166 .reg_md32_ddr_en_mask_b = 1,
167
168 /* SPM_SRC2_MASK */
169 .reg_scp_srcclkena_mask_b = 1,
170 .reg_scp_infra_req_mask_b = 1,
171 .reg_scp_apsrc_req_mask_b = 1,
172 .reg_scp_vrf18_req_mask_b = 1,
173 .reg_scp_ddr_en_mask_b = 1,
174 .reg_audio_dsp_srcclkena_mask_b = 1,
175 .reg_audio_dsp_infra_req_mask_b = 1,
176 .reg_audio_dsp_apsrc_req_mask_b = 1,
177 .reg_audio_dsp_vrf18_req_mask_b = 1,
178 .reg_audio_dsp_ddr_en_mask_b = 1,
179 .reg_ufs_srcclkena_mask_b = 1,
180 .reg_ufs_infra_req_mask_b = 1,
181 .reg_ufs_apsrc_req_mask_b = 1,
182 .reg_ufs_vrf18_req_mask_b = 1,
183 .reg_ufs_ddr_en_mask_b = 1,
184 .reg_disp0_apsrc_req_mask_b = 1,
185 .reg_disp0_ddr_en_mask_b = 1,
186 .reg_disp1_apsrc_req_mask_b = 1,
187 .reg_disp1_ddr_en_mask_b = 1,
188 .reg_gce_infra_req_mask_b = 1,
189 .reg_gce_apsrc_req_mask_b = 1,
190 .reg_gce_vrf18_req_mask_b = 1,
191 .reg_gce_ddr_en_mask_b = 1,
192 .reg_apu_srcclkena_mask_b = 1,
193 .reg_apu_infra_req_mask_b = 1,
194 .reg_apu_apsrc_req_mask_b = 1,
195 .reg_apu_vrf18_req_mask_b = 1,
196 .reg_apu_ddr_en_mask_b = 1,
197 .reg_cg_check_srcclkena_mask_b = 0,
198 .reg_cg_check_apsrc_req_mask_b = 0,
199 .reg_cg_check_vrf18_req_mask_b = 0,
200 .reg_cg_check_ddr_en_mask_b = 0,
201
202 /* SPM_SRC3_MASK */
203 .reg_dvfsrc_event_trigger_mask_b = 1,
204 .reg_sw2spm_int0_mask_b = 0,
205 .reg_sw2spm_int1_mask_b = 0,
206 .reg_sw2spm_int2_mask_b = 0,
207 .reg_sw2spm_int3_mask_b = 0,
208 .reg_sc_adsp2spm_wakeup_mask_b = 0,
209 .reg_sc_sspm2spm_wakeup_mask_b = 0,
210 .reg_sc_scp2spm_wakeup_mask_b = 0,
211 .reg_csyspwrreq_mask = 1,
212 .reg_spm_srcclkena_reserved_mask_b = 0,
213 .reg_spm_infra_req_reserved_mask_b = 0,
214 .reg_spm_apsrc_req_reserved_mask_b = 0,
215 .reg_spm_vrf18_req_reserved_mask_b = 0,
216 .reg_spm_ddr_en_reserved_mask_b = 0,
217 .reg_mcupm_srcclkena_mask_b = 1,
218 .reg_mcupm_infra_req_mask_b = 1,
219 .reg_mcupm_apsrc_req_mask_b = 1,
220 .reg_mcupm_vrf18_req_mask_b = 1,
221 .reg_mcupm_ddr_en_mask_b = 1,
222 .reg_msdc0_srcclkena_mask_b = 1,
223 .reg_msdc0_infra_req_mask_b = 1,
224 .reg_msdc0_apsrc_req_mask_b = 1,
225 .reg_msdc0_vrf18_req_mask_b = 1,
226 .reg_msdc0_ddr_en_mask_b = 1,
227 .reg_msdc1_srcclkena_mask_b = 1,
228 .reg_msdc1_infra_req_mask_b = 1,
229 .reg_msdc1_apsrc_req_mask_b = 1,
230 .reg_msdc1_vrf18_req_mask_b = 1,
231 .reg_msdc1_ddr_en_mask_b = 1,
232
233 /* SPM_SRC4_MASK */
234 .ccif_event_mask_b = 0xFFF,
235 .reg_bak_psri_srcclkena_mask_b = 0,
236 .reg_bak_psri_infra_req_mask_b = 0,
237 .reg_bak_psri_apsrc_req_mask_b = 0,
238 .reg_bak_psri_vrf18_req_mask_b = 0,
239 .reg_bak_psri_ddr_en_mask_b = 0,
240 .reg_dramc0_md32_infra_req_mask_b = 1,
241 .reg_dramc0_md32_vrf18_req_mask_b = 0,
242 .reg_dramc1_md32_infra_req_mask_b = 1,
243 .reg_dramc1_md32_vrf18_req_mask_b = 0,
244 .reg_conn_srcclkenb2pwrap_mask_b = 0,
245 .reg_dramc0_md32_wakeup_mask = 1,
246 .reg_dramc1_md32_wakeup_mask = 1,
247
248 /* SPM_SRC5_MASK */
249 .reg_mcusys_merge_apsrc_req_mask_b = 0x11,
250 .reg_mcusys_merge_ddr_en_mask_b = 0x11,
251 .reg_msdc2_srcclkena_mask_b = 1,
252 .reg_msdc2_infra_req_mask_b = 1,
253 .reg_msdc2_apsrc_req_mask_b = 1,
254 .reg_msdc2_vrf18_req_mask_b = 1,
255 .reg_msdc2_ddr_en_mask_b = 1,
256 .reg_pcie_srcclkena_mask_b = 1,
257 .reg_pcie_infra_req_mask_b = 1,
258 .reg_pcie_apsrc_req_mask_b = 1,
259 .reg_pcie_vrf18_req_mask_b = 1,
260 .reg_pcie_ddr_en_mask_b = 1,
261
262 /* SPM_WAKEUP_EVENT_MASK */
263 .reg_wakeup_event_mask = 0xEFFFFFFF,
264
265 /* SPM_WAKEUP_EVENT_EXT_MASK */
266 .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
267
268 /* Auto-gen End */
269 };
270
271 struct spm_lp_scen __spm_vcorefs = {
272 .pwrctrl = &vcorefs_ctrl,
273 };
274
spm_vcorefs_pwarp_cmd(uint64_t cmd,uint64_t val)275 static void spm_vcorefs_pwarp_cmd(uint64_t cmd, uint64_t val)
276 {
277 if (cmd < NR_IDX_ALL) {
278 mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val);
279 } else {
280 INFO("cmd out of range!\n");
281 }
282 }
283
spm_dvfsfw_init(uint64_t boot_up_opp,uint64_t dram_issue)284 void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue)
285 {
286 mmio_clrsetbits_32(SPM_DVFS_MISC, SPM_DVFS_FORCE_ENABLE_LSB,
287 SPM_DVFSRC_ENABLE_LSB);
288
289 mmio_write_32(SPM_DVFS_LEVEL, 0x00000001);
290 mmio_write_32(SPM_DVS_DFS_LEVEL, 0x00010001);
291 }
292
__spm_sync_vcore_dvfs_power_control(struct pwr_ctrl * dest_pwr_ctrl,const struct pwr_ctrl * src_pwr_ctrl)293 void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
294 const struct pwr_ctrl *src_pwr_ctrl)
295 {
296 uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS |
297 SPM_FLAG_DISABLE_VCORE_DFS |
298 SPM_FLAG_ENABLE_VOLTAGE_BIN;
299
300 dest_pwr_ctrl->pcm_flags = (dest_pwr_ctrl->pcm_flags & (~dvfs_mask)) |
301 (src_pwr_ctrl->pcm_flags & dvfs_mask);
302
303 if (dest_pwr_ctrl->pcm_flags_cust > 0U) {
304 dest_pwr_ctrl->pcm_flags_cust =
305 (dest_pwr_ctrl->pcm_flags_cust & (~dvfs_mask)) |
306 (src_pwr_ctrl->pcm_flags & dvfs_mask);
307 }
308 }
309
spm_go_to_vcorefs(void)310 static void spm_go_to_vcorefs(void)
311 {
312 __spm_set_power_control(__spm_vcorefs.pwrctrl);
313 __spm_set_wakeup_event(__spm_vcorefs.pwrctrl);
314 __spm_set_pcm_flags(__spm_vcorefs.pwrctrl);
315 __spm_send_cpu_wakeup_event();
316 }
317
dvfsrc_init(void)318 static void dvfsrc_init(void)
319 {
320 uint32_t i;
321
322 for (i = 0U; i < ARRAY_SIZE(dvfsrc_init_configs); i++) {
323 mmio_write_32(dvfsrc_init_configs[i].offset,
324 dvfsrc_init_configs[i].val);
325 }
326 }
327
spm_vcorefs_get_efuse_data(void)328 static uint32_t spm_vcorefs_get_efuse_data(void)
329 {
330 return mmio_read_32(VCORE_VB_EFUSE);
331 }
332
is_rising_need(void)333 static uint32_t is_rising_need(void)
334 {
335 return ((spm_vcorefs_get_efuse_data() & 0xF) == 11U) ? 1U : 0U;
336 }
337
spm_vcorefs_vcore_setting(uint64_t flag)338 static void spm_vcorefs_vcore_setting(uint64_t flag)
339 {
340 uint32_t dvfs_v_mode, dvfsrc_rsrv, i;
341 uint32_t opp_uv[] = {725000U, 650000U, 600000U, 575000U};
342
343 dvfsrc_rsrv = mmio_read_32(DVFSRC_RSRV_4);
344
345 dvfs_v_mode = (dvfsrc_rsrv >> V_VMODE_SHIFT) & 0x3;
346
347 if (is_rising_need() != 0U) {
348 opp_uv[2] = 625000U;
349 opp_uv[3] = 600000U;
350 }
351
352 for (i = 0; i < ARRAY_SIZE(opp_uv); i++) {
353 if (dvfs_v_mode == 3U) {
354 /* LV */
355 opp_uv[i] = round_down((opp_uv[i] * VCORE_LV) / 100U,
356 PMIC_STEP_UV);
357 } else if (dvfs_v_mode == 1U) {
358 /* HV */
359 opp_uv[i] = round_up((opp_uv[i] * VCORE_HV) / 100U,
360 PMIC_STEP_UV);
361 }
362 spm_vcorefs_pwarp_cmd(i, __vcore_uv_to_pmic(opp_uv[i]));
363 }
364 }
365
spm_vcorefs_args(uint64_t x1,uint64_t x2,uint64_t x3,uint64_t * x4)366 uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4)
367 {
368 uint64_t cmd = x1;
369 uint64_t spm_flags;
370
371 switch (cmd) {
372 case VCOREFS_SMC_CMD_INIT:
373 /* vcore_dvfs init + kick */
374 mmio_write_32(DVFSRC_SW_REQ5, SW_REQ5_INIT_VAL);
375 spm_dvfsfw_init(0ULL, 0ULL);
376 spm_vcorefs_vcore_setting(x3 & 0xF);
377 spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
378 if ((x2 & 0x1) > 0U) {
379 spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
380 }
381
382 if ((x2 & 0x2) > 0U) {
383 spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
384 }
385
386 if ((mmio_read_32(DVFSRC_RSRV_4) & VCORE_CT_ENABLE) > 0U) {
387 spm_flags |= SPM_FLAG_ENABLE_VOLTAGE_BIN;
388 }
389
390 set_pwrctrl_pcm_flags(__spm_vcorefs.pwrctrl, spm_flags);
391 spm_go_to_vcorefs();
392 dvfsrc_init();
393
394 *x4 = 0U;
395 mmio_write_32(DVFSRC_SW_REQ5, 0U);
396 break;
397 case VCOREFS_SMC_CMD_KICK:
398 mmio_write_32(DVFSRC_SW_REQ5, 0U);
399 break;
400 default:
401 break;
402 }
403
404 return 0ULL;
405 }
406