1 /* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #define PLAT_PRIMARY_CPU 0x0 11 12 #define MT_GIC_BASE (0x0C000000) 13 #define MCUCFG_BASE (0x0C530000) 14 #define IO_PHYS (0x10000000) 15 16 /* Aggregate of all devices for MMU mapping */ 17 #define MTK_DEV_RNG0_BASE IO_PHYS 18 #define MTK_DEV_RNG0_SIZE 0x10000000 19 #define MTK_DEV_RNG2_BASE MT_GIC_BASE 20 #define MTK_DEV_RNG2_SIZE 0x600000 21 #define MTK_MCDI_SRAM_BASE 0x11B000 22 #define MTK_MCDI_SRAM_MAP_SIZE 0x1000 23 24 #define TOPCKGEN_BASE (IO_PHYS + 0x00000000) 25 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 26 #define SPM_BASE (IO_PHYS + 0x00006000) 27 #define RGU_BASE (IO_PHYS + 0x00007000) 28 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 29 #define DRM_BASE (IO_PHYS + 0x0000D000) 30 #define SSPM_MBOX_BASE (IO_PHYS + 0x00480000) 31 #define PERICFG_AO_BASE (IO_PHYS + 0x01003000) 32 #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 33 #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 34 #define VDOSYS0_BASE (IO_PHYS + 0x0C01A000) 35 #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 36 #define DVFSRC_BASE (IO_PHYS + 0x00012000) 37 38 /******************************************************************************* 39 * DP/eDP related constants 40 ******************************************************************************/ 41 #define eDP_SEC_BASE (IO_PHYS + 0x0C504000) 42 #define DP_SEC_BASE (IO_PHYS + 0x0C604000) 43 #define eDP_SEC_SIZE 0x1000 44 #define DP_SEC_SIZE 0x1000 45 46 /******************************************************************************* 47 * GPIO related constants 48 ******************************************************************************/ 49 #define GPIO_BASE (IO_PHYS + 0x00005000) 50 #define IOCFG_BM_BASE (IO_PHYS + 0x01D10000) 51 #define IOCFG_BL_BASE (IO_PHYS + 0x01D30000) 52 #define IOCFG_BR_BASE (IO_PHYS + 0x01D40000) 53 #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 54 #define IOCFG_RB_BASE (IO_PHYS + 0x01EB0000) 55 #define IOCFG_TL_BASE (IO_PHYS + 0x01F40000) 56 57 /******************************************************************************* 58 * UART related constants 59 ******************************************************************************/ 60 #define UART0_BASE (IO_PHYS + 0x01001100) 61 #define UART1_BASE (IO_PHYS + 0x01001200) 62 63 #define UART_BAUDRATE 115200 64 65 /******************************************************************************* 66 * PMIC related constants 67 ******************************************************************************/ 68 #define PMIC_WRAP_BASE (IO_PHYS + 0x00024000) 69 70 /******************************************************************************* 71 * EMI MPU related constants 72 ******************************************************************************/ 73 #define EMI_MPU_BASE (IO_PHYS + 0x00226000) 74 #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000) 75 76 /******************************************************************************* 77 * System counter frequency related constants 78 ******************************************************************************/ 79 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 80 #define SYS_COUNTER_FREQ_IN_MHZ 13 81 82 /******************************************************************************* 83 * GIC-600 & interrupt handling related constants 84 ******************************************************************************/ 85 /* Base MTK_platform compatible GIC memory map */ 86 #define BASE_GICD_BASE MT_GIC_BASE 87 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 88 89 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 90 #define CIRQ_REG_NUM 23 91 #define CIRQ_IRQ_NUM 730 92 #define CIRQ_SPI_START 96 93 #define MD_WDT_IRQ_BIT_ID 141 94 /******************************************************************************* 95 * Platform binary types for linking 96 ******************************************************************************/ 97 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 98 #define PLATFORM_LINKER_ARCH aarch64 99 100 /******************************************************************************* 101 * Generic platform constants 102 ******************************************************************************/ 103 #define PLATFORM_STACK_SIZE 0x800 104 105 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 106 107 #define PLAT_MAX_PWR_LVL U(3) 108 #define PLAT_MAX_RET_STATE U(1) 109 #define PLAT_MAX_OFF_STATE U(9) 110 111 #define PLATFORM_SYSTEM_COUNT U(1) 112 #define PLATFORM_MCUSYS_COUNT U(1) 113 #define PLATFORM_CLUSTER_COUNT U(1) 114 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 115 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 116 117 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 118 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 119 120 #define SOC_CHIP_ID U(0x8195) 121 122 /******************************************************************************* 123 * Platform memory map related constants 124 ******************************************************************************/ 125 #define TZRAM_BASE 0x54600000 126 #define TZRAM_SIZE 0x00030000 127 128 /******************************************************************************* 129 * BL31 specific defines. 130 ******************************************************************************/ 131 /* 132 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 133 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 134 * little space for growth. 135 */ 136 #define BL31_BASE (TZRAM_BASE + 0x1000) 137 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 138 139 /******************************************************************************* 140 * Platform specific page table and MMU setup constants 141 ******************************************************************************/ 142 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 143 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 144 #define MAX_XLAT_TABLES 16 145 #define MAX_MMAP_REGIONS 16 146 147 /******************************************************************************* 148 * Declarations and constants to access the mailboxes safely. Each mailbox is 149 * aligned on the biggest cache line size in the platform. This is known only 150 * to the platform as it might have a combination of integrated and external 151 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 152 * line at any cache level. They could belong to different cpus/clusters & 153 * get written while being protected by different locks causing corruption of 154 * a valid mailbox address. 155 ******************************************************************************/ 156 #define CACHE_WRITEBACK_SHIFT 6 157 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 158 #endif /* PLATFORM_DEF_H */ 159