1 /*
2 * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /* common headers */
8 #include <assert.h>
9
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <drivers/gpio.h>
13 #include <lib/psci/psci.h>
14
15 /* platform specific headers */
16 #include <mt_gic_v3.h>
17 #include <mtk_ptp3_common.h>
18 #include <mtspmc.h>
19 #include <plat/common/platform.h>
20 #include <plat_dfd.h>
21 #include <plat_mtk_lpm.h>
22 #include <plat_params.h>
23 #include <plat_pm.h>
24 #include <pmic.h>
25 #include <rtc.h>
26
27 /*
28 * Cluster state request:
29 * [0] : The CPU requires cluster power down
30 * [1] : The CPU requires cluster power on
31 */
32 #define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff)
33 #define coordinate_cluster_pwron() coordinate_cluster(1)
34 #define coordinate_cluster_pwroff() coordinate_cluster(0)
35
36 /* platform secure entry point */
37 static uintptr_t secure_entrypoint;
38 /* per-CPU power state */
39 static unsigned int plat_power_state[PLATFORM_CORE_COUNT];
40
41 /* platform CPU power domain - ops */
42 static const struct mt_lpm_tz *plat_mt_pm;
43
44 #define plat_mt_pm_invoke(_name, _cpu, _state) ({ \
45 int ret = -1; \
46 if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
47 ret = plat_mt_pm->_name(_cpu, _state); \
48 } \
49 ret; })
50
51 #define plat_mt_pm_invoke_no_check(_name, _cpu, _state) ({ \
52 if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
53 (void) plat_mt_pm->_name(_cpu, _state); \
54 } \
55 })
56
57 /*
58 * Common MTK_platform operations to power on/off a
59 * CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
60 */
61
plat_cpu_pwrdwn_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)62 static void plat_cpu_pwrdwn_common(unsigned int cpu,
63 const psci_power_state_t *state, unsigned int req_pstate)
64 {
65 assert(cpu == plat_my_core_pos());
66
67 plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state);
68
69 if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) ||
70 (req_pstate == 0U)) { /* hotplug off */
71 coordinate_cluster_pwroff();
72 }
73
74 /* Prevent interrupts from spuriously waking up this CPU */
75 mt_gic_rdistif_save();
76 gicv3_cpuif_disable(cpu);
77 gicv3_rdistif_off(cpu);
78 }
79
plat_cpu_pwron_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)80 static void plat_cpu_pwron_common(unsigned int cpu,
81 const psci_power_state_t *state, unsigned int req_pstate)
82 {
83 assert(cpu == plat_my_core_pos());
84
85 plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state);
86
87 coordinate_cluster_pwron();
88
89 /* PTP3 config */
90 ptp3_core_init(cpu);
91
92 /*
93 * If mcusys does power down before then restore
94 * all CPUs' GIC Redistributors
95 */
96 if (IS_MCUSYS_OFF_STATE(state)) {
97 mt_gic_rdistif_restore_all();
98 } else {
99 gicv3_rdistif_on(cpu);
100 gicv3_cpuif_enable(cpu);
101 mt_gic_rdistif_init();
102 mt_gic_rdistif_restore();
103 }
104 }
105
106 /*
107 * Common MTK_platform operations to power on/off a
108 * cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
109 */
110
plat_cluster_pwrdwn_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)111 static void plat_cluster_pwrdwn_common(unsigned int cpu,
112 const psci_power_state_t *state, unsigned int req_pstate)
113 {
114 assert(cpu == plat_my_core_pos());
115
116 if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) {
117 coordinate_cluster_pwron();
118
119 /* TODO: return on fail.
120 * Add a 'return' here before adding any code following
121 * the if-block.
122 */
123 }
124 }
125
plat_cluster_pwron_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)126 static void plat_cluster_pwron_common(unsigned int cpu,
127 const psci_power_state_t *state, unsigned int req_pstate)
128 {
129 assert(cpu == plat_my_core_pos());
130
131 if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) {
132 /* TODO: return on fail.
133 * Add a 'return' here before adding any code following
134 * the if-block.
135 */
136 }
137 }
138
139 /*
140 * Common MTK_platform operations to power on/off a
141 * mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
142 */
143
plat_mcusys_pwrdwn_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)144 static void plat_mcusys_pwrdwn_common(unsigned int cpu,
145 const psci_power_state_t *state, unsigned int req_pstate)
146 {
147 assert(cpu == plat_my_core_pos());
148
149 if (plat_mt_pm_invoke(pwr_mcusys_dwn, cpu, state) != 0) {
150 return; /* return on fail */
151 }
152
153 mt_gic_distif_save();
154 gic_sgi_save_all();
155 }
156
plat_mcusys_pwron_common(unsigned int cpu,const psci_power_state_t * state,unsigned int req_pstate)157 static void plat_mcusys_pwron_common(unsigned int cpu,
158 const psci_power_state_t *state, unsigned int req_pstate)
159 {
160 assert(cpu == plat_my_core_pos());
161
162 if (plat_mt_pm_invoke(pwr_mcusys_on, cpu, state) != 0) {
163 return; /* return on fail */
164 }
165
166 mt_gic_init();
167 mt_gic_distif_restore();
168 gic_sgi_restore_all();
169
170 dfd_resume();
171
172 plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state);
173 }
174
175 /*
176 * plat_psci_ops implementation
177 */
178
plat_cpu_standby(plat_local_state_t cpu_state)179 static void plat_cpu_standby(plat_local_state_t cpu_state)
180 {
181 uint64_t scr;
182
183 scr = read_scr_el3();
184 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
185
186 isb();
187 dsb();
188 wfi();
189
190 write_scr_el3(scr);
191 }
192
plat_power_domain_on(u_register_t mpidr)193 static int plat_power_domain_on(u_register_t mpidr)
194 {
195 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
196 unsigned int cluster = 0U;
197
198 if (cpu >= PLATFORM_CORE_COUNT) {
199 return PSCI_E_INVALID_PARAMS;
200 }
201
202 if (!spm_get_cluster_powerstate(cluster)) {
203 spm_poweron_cluster(cluster);
204 }
205
206 /* init CPU reset arch as AARCH64 */
207 mcucfg_init_archstate(cluster, cpu, true);
208 mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
209 spm_poweron_cpu(cluster, cpu);
210
211 return PSCI_E_SUCCESS;
212 }
213
plat_power_domain_on_finish(const psci_power_state_t * state)214 static void plat_power_domain_on_finish(const psci_power_state_t *state)
215 {
216 unsigned long mpidr = read_mpidr_el1();
217 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
218
219 assert(cpu < PLATFORM_CORE_COUNT);
220
221 /* Allow IRQs to wakeup this core in IDLE flow */
222 mcucfg_enable_gic_wakeup(0U, cpu);
223
224 if (IS_CLUSTER_OFF_STATE(state)) {
225 plat_cluster_pwron_common(cpu, state, 0U);
226 }
227
228 plat_cpu_pwron_common(cpu, state, 0U);
229 }
230
plat_power_domain_off(const psci_power_state_t * state)231 static void plat_power_domain_off(const psci_power_state_t *state)
232 {
233 unsigned long mpidr = read_mpidr_el1();
234 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
235
236 assert(cpu < PLATFORM_CORE_COUNT);
237
238 plat_cpu_pwrdwn_common(cpu, state, 0U);
239 spm_poweroff_cpu(0U, cpu);
240
241 /* prevent unintended IRQs from waking up the hot-unplugged core */
242 mcucfg_disable_gic_wakeup(0U, cpu);
243
244 if (IS_CLUSTER_OFF_STATE(state)) {
245 plat_cluster_pwrdwn_common(cpu, state, 0U);
246 }
247 }
248
plat_power_domain_suspend(const psci_power_state_t * state)249 static void plat_power_domain_suspend(const psci_power_state_t *state)
250 {
251 unsigned int cpu = plat_my_core_pos();
252
253 assert(cpu < PLATFORM_CORE_COUNT);
254
255 plat_mt_pm_invoke_no_check(pwr_prompt, cpu, state);
256
257 /* Perform the common CPU specific operations */
258 plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]);
259
260 if (IS_CLUSTER_OFF_STATE(state)) {
261 /* Perform the common cluster specific operations */
262 plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]);
263 }
264
265 if (IS_MCUSYS_OFF_STATE(state)) {
266 /* Perform the common mcusys specific operations */
267 plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]);
268 }
269 }
270
plat_power_domain_suspend_finish(const psci_power_state_t * state)271 static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
272 {
273 unsigned int cpu = plat_my_core_pos();
274
275 assert(cpu < PLATFORM_CORE_COUNT);
276
277 if (IS_MCUSYS_OFF_STATE(state)) {
278 /* Perform the common mcusys specific operations */
279 plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]);
280 }
281
282 if (IS_CLUSTER_OFF_STATE(state)) {
283 /* Perform the common cluster specific operations */
284 plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]);
285 }
286
287 /* Perform the common CPU specific operations */
288 plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]);
289
290 plat_mt_pm_invoke_no_check(pwr_reflect, cpu, state);
291 }
292
plat_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)293 static int plat_validate_power_state(unsigned int power_state,
294 psci_power_state_t *req_state)
295 {
296 unsigned int pstate = psci_get_pstate_type(power_state);
297 unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state);
298 unsigned int cpu = plat_my_core_pos();
299
300 if (aff_lvl > PLAT_MAX_PWR_LVL) {
301 return PSCI_E_INVALID_PARAMS;
302 }
303
304 if (pstate == PSTATE_TYPE_STANDBY) {
305 req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE;
306 } else {
307 unsigned int i;
308 unsigned int pstate_id = psci_get_pstate_id(power_state);
309 plat_local_state_t s = MTK_LOCAL_STATE_OFF;
310
311 /* Use pstate_id to be power domain state */
312 if (pstate_id > s) {
313 s = (plat_local_state_t)pstate_id;
314 }
315
316 for (i = 0U; i <= aff_lvl; i++) {
317 req_state->pwr_domain_state[i] = s;
318 }
319 }
320
321 plat_power_state[cpu] = power_state;
322 return PSCI_E_SUCCESS;
323 }
324
plat_get_sys_suspend_power_state(psci_power_state_t * req_state)325 static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
326 {
327 unsigned int lv;
328 unsigned int cpu = plat_my_core_pos();
329
330 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) {
331 req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE;
332 }
333
334 plat_power_state[cpu] =
335 psci_make_powerstate(
336 MT_PLAT_PWR_STATE_SYSTEM_SUSPEND,
337 PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL);
338
339 flush_dcache_range((uintptr_t)
340 &plat_power_state[cpu],
341 sizeof(plat_power_state[cpu]));
342 }
343
344 /*******************************************************************************
345 * MTK handlers to shutdown/reboot the system
346 ******************************************************************************/
plat_mtk_system_reset(void)347 static void __dead2 plat_mtk_system_reset(void)
348 {
349 struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset();
350
351 INFO("MTK System Reset\n");
352
353 gpio_set_value(gpio_reset->index, gpio_reset->polarity);
354
355 wfi();
356 ERROR("MTK System Reset: operation not handled.\n");
357 panic();
358 }
359
plat_mtk_system_off(void)360 static void __dead2 plat_mtk_system_off(void)
361 {
362 INFO("MTK System Off\n");
363
364 rtc_power_off_sequence();
365 pmic_power_off();
366
367 wfi();
368 ERROR("MTK System Off: operation not handled.\n");
369 panic();
370 }
371
372 static const plat_psci_ops_t plat_psci_ops = {
373 .system_reset = plat_mtk_system_reset,
374 .system_off = plat_mtk_system_off,
375 .cpu_standby = plat_cpu_standby,
376 .pwr_domain_on = plat_power_domain_on,
377 .pwr_domain_on_finish = plat_power_domain_on_finish,
378 .pwr_domain_off = plat_power_domain_off,
379 .pwr_domain_suspend = plat_power_domain_suspend,
380 .pwr_domain_suspend_finish = plat_power_domain_suspend_finish,
381 .validate_power_state = plat_validate_power_state,
382 .get_sys_suspend_power_state = plat_get_sys_suspend_power_state
383 };
384
plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)385 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
386 const plat_psci_ops_t **psci_ops)
387 {
388 *psci_ops = &plat_psci_ops;
389 secure_entrypoint = sec_entrypoint;
390
391 /*
392 * init the warm reset config for boot CPU
393 * reset arch as AARCH64
394 * reset addr as function bl31_warm_entrypoint()
395 */
396 mcucfg_init_archstate(0U, 0U, true);
397 mcucfg_set_bootaddr(0U, 0U, secure_entrypoint);
398
399 spmc_init();
400 plat_mt_pm = mt_plat_cpu_pm_init();
401
402 return 0;
403 }
404