1/*
2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2015-2020, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef PLAT_MACROS_S
9#define PLAT_MACROS_S
10
11#include <drivers/arm/gicv2.h>
12#include <tegra_def.h>
13
14.section .rodata.gic_reg_name, "aS"
15gicc_regs:
16	.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
17gicd_pend_reg:
18	.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
19newline:
20	.asciz "\n"
21spacer:
22	.asciz ":\t\t0x"
23
24/* ---------------------------------------------
25 * The below macro prints out relevant GIC
26 * registers whenever an unhandled exception is
27 * taken in BL31.
28 * ---------------------------------------------
29 */
30.macro plat_crash_print_regs
31#ifdef TEGRA_GICC_BASE
32	mov_imm	x16, TEGRA_GICC_BASE
33
34	/* gicc base address is now in x16 */
35	adr	x6, gicc_regs	/* Load the gicc reg list to x6 */
36	/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
37	ldr	w8, [x16, #GICC_HPPIR]
38	ldr	w9, [x16, #GICC_AHPPIR]
39	ldr	w10, [x16, #GICC_CTLR]
40	/* Store to the crash buf and print to cosole */
41	bl	str_in_crash_buf_print
42#endif
43	/* Print the GICD_ISPENDR regs */
44	mov_imm	x16, TEGRA_GICD_BASE
45	add	x7, x16, #GICD_ISPENDR
46	adr	x4, gicd_pend_reg
47	bl	asm_print_str
482:
49	sub	x4, x7, x16
50	cmp	x4, #0x280
51	b.eq	1f
52	bl	asm_print_hex
53	adr	x4, spacer
54	bl	asm_print_str
55	ldr	w4, [x7], #4
56	bl	asm_print_hex
57	adr	x4, newline
58	bl	asm_print_str
59	b	2b
601:
61.endm
62
63#endif /* PLAT_MACROS_S */
64