1 /*
2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <errno.h>
10 #include <inttypes.h>
11 #include <stdint.h>
12 #include <string.h>
13
14 #include <arch.h>
15 #include <arch_helpers.h>
16 #include <common/bl_common.h>
17 #include <common/debug.h>
18 #include <context.h>
19 #include <denver.h>
20 #include <lib/el3_runtime/context_mgmt.h>
21 #include <lib/mmio.h>
22
23 #include <mce.h>
24 #include <mce_private.h>
25 #include <t18x_ari.h>
26 #include <tegra_def.h>
27 #include <tegra_platform.h>
28
29 /* NVG functions handlers */
30 static arch_mce_ops_t nvg_mce_ops = {
31 .enter_cstate = nvg_enter_cstate,
32 .update_cstate_info = nvg_update_cstate_info,
33 .update_crossover_time = nvg_update_crossover_time,
34 .read_cstate_stats = nvg_read_cstate_stats,
35 .write_cstate_stats = nvg_write_cstate_stats,
36 .call_enum_misc = ari_enumeration_misc,
37 .is_ccx_allowed = nvg_is_ccx_allowed,
38 .is_sc7_allowed = nvg_is_sc7_allowed,
39 .online_core = nvg_online_core,
40 .cc3_ctrl = nvg_cc3_ctrl,
41 .update_reset_vector = ari_reset_vector_update,
42 .roc_flush_cache = ari_roc_flush_cache,
43 .roc_flush_cache_trbits = ari_roc_flush_cache_trbits,
44 .roc_clean_cache = ari_roc_clean_cache,
45 .read_write_mca = ari_read_write_mca,
46 .update_ccplex_gsc = ari_update_ccplex_gsc,
47 .enter_ccplex_state = ari_enter_ccplex_state,
48 .read_write_uncore_perfmon = ari_read_write_uncore_perfmon,
49 .misc_ccplex = ari_misc_ccplex
50 };
51
52 /* ARI functions handlers */
53 static arch_mce_ops_t ari_mce_ops = {
54 .enter_cstate = ari_enter_cstate,
55 .update_cstate_info = ari_update_cstate_info,
56 .update_crossover_time = ari_update_crossover_time,
57 .read_cstate_stats = ari_read_cstate_stats,
58 .write_cstate_stats = ari_write_cstate_stats,
59 .call_enum_misc = ari_enumeration_misc,
60 .is_ccx_allowed = ari_is_ccx_allowed,
61 .is_sc7_allowed = ari_is_sc7_allowed,
62 .online_core = ari_online_core,
63 .cc3_ctrl = ari_cc3_ctrl,
64 .update_reset_vector = ari_reset_vector_update,
65 .roc_flush_cache = ari_roc_flush_cache,
66 .roc_flush_cache_trbits = ari_roc_flush_cache_trbits,
67 .roc_clean_cache = ari_roc_clean_cache,
68 .read_write_mca = ari_read_write_mca,
69 .update_ccplex_gsc = ari_update_ccplex_gsc,
70 .enter_ccplex_state = ari_enter_ccplex_state,
71 .read_write_uncore_perfmon = ari_read_write_uncore_perfmon,
72 .misc_ccplex = ari_misc_ccplex
73 };
74
75 typedef struct {
76 uint32_t ari_base;
77 arch_mce_ops_t *ops;
78 } mce_config_t;
79
80 /* Table to hold the per-CPU ARI base address and function handlers */
81 static mce_config_t mce_cfg_table[MCE_ARI_APERTURES_MAX] = {
82 {
83 /* A57 Core 0 */
84 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_0_OFFSET,
85 .ops = &ari_mce_ops,
86 },
87 {
88 /* A57 Core 1 */
89 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_1_OFFSET,
90 .ops = &ari_mce_ops,
91 },
92 {
93 /* A57 Core 2 */
94 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_2_OFFSET,
95 .ops = &ari_mce_ops,
96 },
97 {
98 /* A57 Core 3 */
99 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_3_OFFSET,
100 .ops = &ari_mce_ops,
101 },
102 {
103 /* D15 Core 0 */
104 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_4_OFFSET,
105 .ops = &nvg_mce_ops,
106 },
107 {
108 /* D15 Core 1 */
109 .ari_base = TEGRA_MMCRAB_BASE + MCE_ARI_APERTURE_5_OFFSET,
110 .ops = &nvg_mce_ops,
111 }
112 };
113
mce_get_curr_cpu_ari_base(void)114 static uint32_t mce_get_curr_cpu_ari_base(void)
115 {
116 uint64_t mpidr = read_mpidr();
117 uint64_t cpuid = mpidr & MPIDR_CPU_MASK;
118 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
119
120 /*
121 * T186 has 2 CPU clusters, one with Denver CPUs and the other with
122 * ARM CortexA-57 CPUs. Each cluster consists of 4 CPUs and the CPU
123 * numbers start from 0. In order to get the proper arch_mce_ops_t
124 * struct, we have to convert the Denver CPU ids to the corresponding
125 * indices in the mce_ops_table array.
126 */
127 if (impl == DENVER_IMPL) {
128 cpuid |= 0x4U;
129 }
130
131 return mce_cfg_table[cpuid].ari_base;
132 }
133
mce_get_curr_cpu_ops(void)134 static arch_mce_ops_t *mce_get_curr_cpu_ops(void)
135 {
136 uint64_t mpidr = read_mpidr();
137 uint64_t cpuid = mpidr & MPIDR_CPU_MASK;
138 uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) &
139 MIDR_IMPL_MASK;
140
141 /*
142 * T186 has 2 CPU clusters, one with Denver CPUs and the other with
143 * ARM CortexA-57 CPUs. Each cluster consists of 4 CPUs and the CPU
144 * numbers start from 0. In order to get the proper arch_mce_ops_t
145 * struct, we have to convert the Denver CPU ids to the corresponding
146 * indices in the mce_ops_table array.
147 */
148 if (impl == DENVER_IMPL) {
149 cpuid |= 0x4U;
150 }
151
152 return mce_cfg_table[cpuid].ops;
153 }
154
155 /*******************************************************************************
156 * Common handler for all MCE commands
157 ******************************************************************************/
mce_command_handler(uint64_t cmd,uint64_t arg0,uint64_t arg1,uint64_t arg2)158 int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
159 uint64_t arg2)
160 {
161 const arch_mce_ops_t *ops;
162 gp_regs_t *gp_regs = get_gpregs_ctx(cm_get_context(NON_SECURE));
163 uint32_t cpu_ari_base;
164 uint64_t ret64 = 0, arg3, arg4, arg5;
165 int32_t ret = 0;
166
167 assert(gp_regs != NULL);
168
169 /* get a pointer to the CPU's arch_mce_ops_t struct */
170 ops = mce_get_curr_cpu_ops();
171
172 /* get the CPU's ARI base address */
173 cpu_ari_base = mce_get_curr_cpu_ari_base();
174
175 switch (cmd) {
176 case (uint64_t)MCE_CMD_ENTER_CSTATE:
177 ret = ops->enter_cstate(cpu_ari_base, arg0, arg1);
178
179 break;
180
181 case (uint64_t)MCE_CMD_UPDATE_CSTATE_INFO:
182 /*
183 * get the parameters required for the update cstate info
184 * command
185 */
186 arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4);
187 arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5);
188 arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6);
189
190 ret = ops->update_cstate_info(cpu_ari_base, (uint32_t)arg0,
191 (uint32_t)arg1, (uint32_t)arg2, (uint8_t)arg3,
192 (uint32_t)arg4, (uint8_t)arg5);
193
194 write_ctx_reg(gp_regs, CTX_GPREG_X4, (0ULL));
195 write_ctx_reg(gp_regs, CTX_GPREG_X5, (0ULL));
196 write_ctx_reg(gp_regs, CTX_GPREG_X6, (0ULL));
197
198 break;
199
200 case (uint64_t)MCE_CMD_UPDATE_CROSSOVER_TIME:
201 ret = ops->update_crossover_time(cpu_ari_base, arg0, arg1);
202
203 break;
204
205 case (uint64_t)MCE_CMD_READ_CSTATE_STATS:
206 ret64 = ops->read_cstate_stats(cpu_ari_base, arg0);
207
208 /* update context to return cstate stats value */
209 write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
210 write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64));
211
212 break;
213
214 case (uint64_t)MCE_CMD_WRITE_CSTATE_STATS:
215 ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1);
216
217 break;
218
219 case (uint64_t)MCE_CMD_IS_CCX_ALLOWED:
220 ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1);
221
222 /* update context to return CCx status value */
223 write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)(ret));
224
225 break;
226
227 case (uint64_t)MCE_CMD_IS_SC7_ALLOWED:
228 ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1);
229
230 /* update context to return SC7 status value */
231 write_ctx_reg(gp_regs, CTX_GPREG_X1, (uint64_t)(ret));
232 write_ctx_reg(gp_regs, CTX_GPREG_X3, (uint64_t)(ret));
233
234 break;
235
236 case (uint64_t)MCE_CMD_ONLINE_CORE:
237 ret = ops->online_core(cpu_ari_base, arg0);
238
239 break;
240
241 case (uint64_t)MCE_CMD_CC3_CTRL:
242 ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2);
243
244 break;
245
246 case (uint64_t)MCE_CMD_ECHO_DATA:
247 ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_ECHO,
248 arg0);
249
250 /* update context to return if echo'd data matched source */
251 write_ctx_reg(gp_regs, CTX_GPREG_X1, ((ret64 == arg0) ?
252 1ULL : 0ULL));
253 write_ctx_reg(gp_regs, CTX_GPREG_X2, ((ret64 == arg0) ?
254 1ULL : 0ULL));
255
256 break;
257
258 case (uint64_t)MCE_CMD_READ_VERSIONS:
259 ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION,
260 arg0);
261
262 /*
263 * version = minor(63:32) | major(31:0). Update context
264 * to return major and minor version number.
265 */
266 write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
267 write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64 >> 32ULL));
268
269 break;
270
271 case (uint64_t)MCE_CMD_ENUM_FEATURES:
272 ret64 = ops->call_enum_misc(cpu_ari_base,
273 TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0);
274
275 /* update context to return features value */
276 write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
277
278 break;
279
280 case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
281 ret = ops->roc_flush_cache_trbits(cpu_ari_base);
282
283 break;
284
285 case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE:
286 ret = ops->roc_flush_cache(cpu_ari_base);
287
288 break;
289
290 case (uint64_t)MCE_CMD_ROC_CLEAN_CACHE:
291 ret = ops->roc_clean_cache(cpu_ari_base);
292
293 break;
294
295 case (uint64_t)MCE_CMD_ENUM_READ_MCA:
296 ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1);
297
298 /* update context to return MCA data/error */
299 write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
300 write_ctx_reg(gp_regs, CTX_GPREG_X2, (arg1));
301 write_ctx_reg(gp_regs, CTX_GPREG_X3, (ret64));
302
303 break;
304
305 case (uint64_t)MCE_CMD_ENUM_WRITE_MCA:
306 ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1);
307
308 /* update context to return MCA error */
309 write_ctx_reg(gp_regs, CTX_GPREG_X1, (ret64));
310 write_ctx_reg(gp_regs, CTX_GPREG_X3, (ret64));
311
312 break;
313
314 #if ENABLE_CHIP_VERIFICATION_HARNESS
315 case (uint64_t)MCE_CMD_ENABLE_LATIC:
316 /*
317 * This call is not for production use. The constant value,
318 * 0xFFFF0000, is specific to allowing for enabling LATIC on
319 * pre-production parts for the chip verification harness.
320 *
321 * Enabling LATIC allows S/W to read the MINI ISPs in the
322 * CCPLEX. The ISMs are used for various measurements relevant
323 * to particular locations in the Silicon. They are small
324 * counters which can be polled to determine how fast a
325 * particular location in the Silicon is.
326 */
327 ops->enter_ccplex_state(mce_get_curr_cpu_ari_base(),
328 0xFFFF0000);
329
330 break;
331 #endif
332
333 case (uint64_t)MCE_CMD_UNCORE_PERFMON_REQ:
334 ret = ops->read_write_uncore_perfmon(cpu_ari_base, arg0, &arg1);
335
336 /* update context to return data */
337 write_ctx_reg(gp_regs, CTX_GPREG_X1, (arg1));
338 break;
339
340 case (uint64_t)MCE_CMD_MISC_CCPLEX:
341 ops->misc_ccplex(cpu_ari_base, arg0, arg1);
342
343 break;
344
345 default:
346 ERROR("unknown MCE command (%" PRIu64 ")\n", cmd);
347 ret = EINVAL;
348 break;
349 }
350
351 return ret;
352 }
353
354 /*******************************************************************************
355 * Handler to update the reset vector for CPUs
356 ******************************************************************************/
mce_update_reset_vector(void)357 int32_t mce_update_reset_vector(void)
358 {
359 const arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
360
361 ops->update_reset_vector(mce_get_curr_cpu_ari_base());
362
363 return 0;
364 }
365
mce_update_ccplex_gsc(tegra_ari_gsc_index_t gsc_idx)366 static int32_t mce_update_ccplex_gsc(tegra_ari_gsc_index_t gsc_idx)
367 {
368 const arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
369
370 ops->update_ccplex_gsc(mce_get_curr_cpu_ari_base(), gsc_idx);
371
372 return 0;
373 }
374
375 /*******************************************************************************
376 * Handler to update carveout values for Video Memory Carveout region
377 ******************************************************************************/
mce_update_gsc_videomem(void)378 int32_t mce_update_gsc_videomem(void)
379 {
380 return mce_update_ccplex_gsc(TEGRA_ARI_GSC_VPR_IDX);
381 }
382
383 /*******************************************************************************
384 * Handler to update carveout values for TZDRAM aperture
385 ******************************************************************************/
mce_update_gsc_tzdram(void)386 int32_t mce_update_gsc_tzdram(void)
387 {
388 return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZ_DRAM_IDX);
389 }
390
391 /*******************************************************************************
392 * Handler to shutdown/reset the entire system
393 ******************************************************************************/
mce_enter_ccplex_state(uint32_t state_idx)394 __dead2 void mce_enter_ccplex_state(uint32_t state_idx)
395 {
396 const arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
397
398 /* sanity check state value */
399 if ((state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) &&
400 (state_idx != TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT)) {
401 panic();
402 }
403
404 ops->enter_ccplex_state(mce_get_curr_cpu_ari_base(), state_idx);
405
406 /* wait till the CCPLEX powers down */
407 for (;;) {
408 ;
409 }
410
411 }
412
413 /*******************************************************************************
414 * Handler to issue the UPDATE_CSTATE_INFO request
415 ******************************************************************************/
mce_update_cstate_info(const mce_cstate_info_t * cstate)416 void mce_update_cstate_info(const mce_cstate_info_t *cstate)
417 {
418 const arch_mce_ops_t *ops = mce_get_curr_cpu_ops();
419
420 /* issue the UPDATE_CSTATE_INFO request */
421 ops->update_cstate_info(mce_get_curr_cpu_ari_base(), cstate->cluster,
422 cstate->ccplex, cstate->system, cstate->system_state_force,
423 cstate->wake_mask, cstate->update_wake_mask);
424 }
425
426 /*******************************************************************************
427 * Handler to read the MCE firmware version and check if it is compatible
428 * with interface header the BL3-1 was compiled against
429 ******************************************************************************/
mce_verify_firmware_version(void)430 void mce_verify_firmware_version(void)
431 {
432 const arch_mce_ops_t *ops;
433 uint32_t cpu_ari_base;
434 uint64_t version;
435 uint32_t major, minor;
436
437 /*
438 * MCE firmware is not supported on simulation platforms.
439 */
440 if (tegra_platform_is_emulation()) {
441
442 INFO("MCE firmware is not supported\n");
443
444 } else {
445 /* get a pointer to the CPU's arch_mce_ops_t struct */
446 ops = mce_get_curr_cpu_ops();
447
448 /* get the CPU's ARI base address */
449 cpu_ari_base = mce_get_curr_cpu_ari_base();
450
451 /*
452 * Read the MCE firmware version and extract the major and minor
453 * version fields
454 */
455 version = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION, 0);
456 major = (uint32_t)version;
457 minor = (uint32_t)(version >> 32);
458
459 INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor,
460 TEGRA_ARI_VERSION_MAJOR, TEGRA_ARI_VERSION_MINOR);
461
462 /*
463 * Verify that the MCE firmware version and the interface header
464 * match
465 */
466 if (major != TEGRA_ARI_VERSION_MAJOR) {
467 ERROR("ARI major version mismatch\n");
468 panic();
469 }
470
471 if (minor < TEGRA_ARI_VERSION_MINOR) {
472 ERROR("ARI minor version mismatch\n");
473 panic();
474 }
475 }
476 }
477