1 /*
2  * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <common/bl_common.h>
9 #include <mce.h>
10 #include <memctrl_v2.h>
11 #include <tegra_platform.h>
12 #include <tegra_private.h>
13 
14 /*******************************************************************************
15  * Array to hold MC context for Tegra194
16  ******************************************************************************/
17 static __attribute__((aligned(16))) mc_regs_t tegra194_mc_context[] = {
18 	_START_OF_TABLE_,
19 	mc_smmu_bypass_cfg,	/* TBU settings */
20 	_END_OF_TABLE_,
21 };
22 
23 /*******************************************************************************
24  * Handler to return the pointer to the MC's context struct
25  ******************************************************************************/
plat_memctrl_get_sys_suspend_ctx(void)26 mc_regs_t *plat_memctrl_get_sys_suspend_ctx(void)
27 {
28 	/* index of _END_OF_TABLE_ */
29 	tegra194_mc_context[0].val = (uint32_t)ARRAY_SIZE(tegra194_mc_context) - 1U;
30 
31 	return tegra194_mc_context;
32 }
33 
34 /*******************************************************************************
35  * Handler to restore platform specific settings to the memory controller
36  ******************************************************************************/
plat_memctrl_restore(void)37 void plat_memctrl_restore(void)
38 {
39 	UNUSED_FUNC_NOP(); /* do nothing */
40 }
41 
42 /*******************************************************************************
43  * Handler to program platform specific settings to the memory controller
44  ******************************************************************************/
plat_memctrl_setup(void)45 void plat_memctrl_setup(void)
46 {
47 	UNUSED_FUNC_NOP(); /* do nothing */
48 }
49 
50 /*******************************************************************************
51  * Handler to program the scratch registers with TZDRAM settings for the
52  * resume firmware
53  ******************************************************************************/
plat_memctrl_tzdram_setup(uint64_t phys_base,uint64_t size_in_bytes)54 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
55 {
56 	uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0);
57 	uint32_t phys_base_lo = (uint32_t)phys_base & 0xFFF00000;
58 	uint32_t phys_base_hi = (uint32_t)(phys_base >> 32);
59 
60 	/*
61 	 * Check TZDRAM carveout register access status. Setup TZDRAM fence
62 	 * only if access is enabled.
63 	 */
64 	if ((sec_reg_ctrl & SECURITY_CFG_WRITE_ACCESS_BIT) ==
65 	     SECURITY_CFG_WRITE_ACCESS_ENABLE) {
66 
67 		/*
68 		 * Setup the Memory controller to allow only secure accesses to
69 		 * the TZDRAM carveout
70 		 */
71 		INFO("Configuring TrustZone DRAM Memory Carveout\n");
72 
73 		tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base_lo);
74 		tegra_mc_write_32(MC_SECURITY_CFG3_0, phys_base_hi);
75 		tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20));
76 
77 		/*
78 		 * MCE propagates the security configuration values across the
79 		 * CCPLEX.
80 		 */
81 		(void)mce_update_gsc_tzdram();
82 	}
83 }
84