1/*
2 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <plat/common/common_def.h>
10#include <memctrl_v2.h>
11#include <tegra_def.h>
12
13#define TEGRA194_STATE_SYSTEM_SUSPEND	0x5C7
14#define TEGRA194_STATE_SYSTEM_RESUME	0x600D
15#define TEGRA194_MC_CTX_SIZE		0xFB
16
17	.align 4
18	.globl	tegra194_cpu_reset_handler
19
20/* CPU reset handler routine */
21func tegra194_cpu_reset_handler
22	/* check if we are exiting system suspend state */
23	adr	x0, __tegra194_system_suspend_state
24	ldr	x1, [x0]
25	mov	x2, #TEGRA194_STATE_SYSTEM_SUSPEND
26	lsl	x2, x2, #16
27	add	x2, x2, #TEGRA194_STATE_SYSTEM_SUSPEND
28	cmp	x1, x2
29	bne	boot_cpu
30
31	/* set system resume state */
32	mov	x1, #TEGRA194_STATE_SYSTEM_RESUME
33	lsl	x1, x1, #16
34	mov	x2, #TEGRA194_STATE_SYSTEM_RESUME
35	add	x1, x1, x2
36	str	x1, [x0]
37	dsb	sy
38
39	/* prepare to relocate to TZSRAM */
40	mov	x0, #BL31_BASE
41	adr	x1, __tegra194_cpu_reset_handler_end
42	adr	x2, __tegra194_cpu_reset_handler_data
43	ldr	x2, [x2, #8]
44
45	/* memcpy16 */
46m_loop16:
47	cmp	x2, #16
48	b.lt	m_loop1
49	ldp	x3, x4, [x1], #16
50	stp	x3, x4, [x0], #16
51	sub	x2, x2, #16
52	b	m_loop16
53	/* copy byte per byte */
54m_loop1:
55	cbz	x2, boot_cpu
56	ldrb	w3, [x1], #1
57	strb	w3, [x0], #1
58	subs	x2, x2, #1
59	b.ne	m_loop1
60
61	/*
62	 * Synchronization barriers to make sure that memory is flushed out
63	 * before we start execution in SysRAM.
64	 */
65	dsb	sy
66	isb
67
68boot_cpu:
69	adr	x0, __tegra194_cpu_reset_handler_data
70	ldr	x0, [x0]
71	br	x0
72endfunc tegra194_cpu_reset_handler
73
74	/*
75	 * Tegra194 reset data (offset 0x0 - 0x2490)
76	 *
77	 * 0x0000: secure world's entrypoint
78	 * 0x0008: BL31 size (RO + RW)
79	 * 0x0010: MC context start
80	 * 0x2490: MC context end
81	 */
82
83	.align 4
84	.type	__tegra194_cpu_reset_handler_data, %object
85	.globl	__tegra194_cpu_reset_handler_data
86__tegra194_cpu_reset_handler_data:
87	.quad	tegra_secure_entrypoint
88	.quad	__BL31_END__ - BL31_BASE
89	.globl	__tegra194_system_suspend_state
90__tegra194_system_suspend_state:
91	.quad	0
92
93	.align 4
94__tegra194_mc_context:
95	.rept	TEGRA194_MC_CTX_SIZE
96	.quad	0
97	.endr
98	.size	__tegra194_cpu_reset_handler_data, \
99		. - __tegra194_cpu_reset_handler_data
100
101	.align 4
102	.globl	__tegra194_cpu_reset_handler_end
103__tegra194_cpu_reset_handler_end:
104
105	.globl tegra194_get_cpu_reset_handler_size
106	.globl tegra194_get_cpu_reset_handler_base
107	.globl tegra194_get_mc_ctx_offset
108	.globl tegra194_set_system_suspend_entry
109
110/* return size of the CPU reset handler */
111func tegra194_get_cpu_reset_handler_size
112	adr	x0, __tegra194_cpu_reset_handler_end
113	adr	x1, tegra194_cpu_reset_handler
114	sub	x0, x0, x1
115	ret
116endfunc tegra194_get_cpu_reset_handler_size
117
118/* return the start address of the CPU reset handler */
119func tegra194_get_cpu_reset_handler_base
120	adr	x0, tegra194_cpu_reset_handler
121	ret
122endfunc tegra194_get_cpu_reset_handler_base
123
124/* return the size of the MC context */
125func tegra194_get_mc_ctx_offset
126	adr	x0, __tegra194_mc_context
127	adr	x1, tegra194_cpu_reset_handler
128	sub	x0, x0, x1
129	ret
130endfunc tegra194_get_mc_ctx_offset
131
132/* set system suspend state before SC7 entry */
133func tegra194_set_system_suspend_entry
134	mov	x0, #TEGRA_MC_BASE
135	mov	x3, #MC_SECURITY_CFG3_0
136	ldr	w1, [x0, x3]
137	lsl	x1, x1, #32
138	mov	x3, #MC_SECURITY_CFG0_0
139	ldr	w2, [x0, x3]
140	orr	x3, x1, x2			/* TZDRAM base */
141	adr	x0, __tegra194_system_suspend_state
142	adr	x1, tegra194_cpu_reset_handler
143	sub	x2, x0, x1			/* offset in TZDRAM */
144	mov	x0, #TEGRA194_STATE_SYSTEM_SUSPEND
145	lsl	x0, x0, #16
146	add	x0, x0, #TEGRA194_STATE_SYSTEM_SUSPEND
147	str	x0, [x3, x2]			/* set value in TZDRAM */
148	dsb	sy
149	ret
150endfunc tegra194_set_system_suspend_entry
151