1 /*
2  * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <common/debug.h>
8 #include <lib/mmio.h>
9 
10 #include <pmc.h>
11 #include <tegra_def.h>
12 
13 #define SB_CSR				0x0
14 #define  SB_CSR_NS_RST_VEC_WR_DIS	(1 << 1)
15 
16 /* CPU reset vector */
17 #define SB_AA64_RESET_LOW		0x30	/* width = 31:0 */
18 #define SB_AA64_RESET_HI		0x34	/* width = 11:0 */
19 
20 extern void tegra_secure_entrypoint(void);
21 
22 /*******************************************************************************
23  * Setup secondary CPU vectors
24  ******************************************************************************/
plat_secondary_setup(void)25 void plat_secondary_setup(void)
26 {
27 	uint32_t val;
28 	uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint;
29 
30 	INFO("Setting up secondary CPU boot\n");
31 
32 	/* setup secondary CPU vector */
33 	mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW,
34 			(reset_addr & 0xFFFFFFFF) | 1);
35 	val = reset_addr >> 32;
36 	mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF);
37 
38 	/* configure PMC */
39 	tegra_pmc_cpu_setup(reset_addr);
40 	tegra_pmc_lock_cpu_vectors();
41 }
42